SLUSD49A September   2017  – January 2019 UCC256303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hybrid Hysteretic Control
      2. 7.3.2  Regulated 12-V Supply
      3. 7.3.3  Feedback Chain
      4. 7.3.4  Optocoupler Feedback Signal Input and Bias
      5. 7.3.5  System External Shut Down
      6. 7.3.6  Pick Lower Block and Soft Start Multiplexer
      7. 7.3.7  Pick Higher Block and Burst Mode Multiplexer
      8. 7.3.8  VCR Comparators
      9. 7.3.9  Resonant Capacitor Voltage Sensing
      10. 7.3.10 Resonant Current Sensing
      11. 7.3.11 Bulk Voltage Sensing
      12. 7.3.12 Output Voltage Sensing
      13. 7.3.13 High Voltage Gate Driver
      14. 7.3.14 Protections
        1. 7.3.14.1 ZCS Region Prevention
        2. 7.3.14.2 Over Current Protection (OCP)
        3. 7.3.14.3 Over Output Voltage Protection (VOUTOVP)
        4. 7.3.14.4 Over Input Voltage Protection (VINOVP)
        5. 7.3.14.5 Under Input Voltage Protection (VINUVP)
        6. 7.3.14.6 Boot UVLO
        7. 7.3.14.7 RVCC UVLO
        8. 7.3.14.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Burst Mode Control
      2. 7.4.2 Soft-Start and Burst-Mode Threshold
      3. 7.4.3 System States and Faults State Machine
      4. 7.4.4 Waveform Generator State Machine
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 BLK Pin Voltage Divider
        16. 8.2.2.16 BW Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 VCR Pin Capacitor Divider
        19. 8.2.2.19 Burst Mode Programming
        20. 8.2.2.20 Soft-Start Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Pin Capacitor
    2. 9.2 Boot Capacitor
    3. 9.3 RVCC Pin Capacitor
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support (if applicable)
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDB|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.4 Waveform Generator State Machine

The waveform generator module consists of a state machine that implements hybrid hysteretic control, adaptive dead time, and ZCS protection. Each cycle of LLC operation is broken down into 4 separate periods: HSON, DTHL, LSON, and DTLH. In addition, there is an IDLE state and a WAKEUP state.

The initial state of this state machine is IDLE. In IDLE state, the system is operating in a low power mode. When WaveGenEn command is received, the state machine enters WAKEUP state to turn on various circuit blocks. Once the WAKEUP timer is expired, the system enters LSON (low side on) state. LSON state is followed by DTLH (dead time high to low) state, which is the dead time state. After DTLH state, the high side turns on and system enters HSON. HSON state is followed by DTHL (dead time low to high) state. After DTHL, the system goes back to LSON state again.

There are minimum and maximum timers in each of the states. The state transition conditions and descriptions are discussed in detail below.

UCC256303 fig52_sluscu6.gifFigure 41. Waveform Generator State Machine Block Diagram

Table 4 summarizes the inputs and outputs of the Waveform Generator State Machine Block Diagram

NOTE

OVP and OCP1 faults are not listed here. But they are processed in the wave gen state machine before handled to system states and faults state machine.

Table 4. Waveform Generator State Machine Inputs and Outputs

SIGNAL NAME I/O DESCRIPTION
IPolarity I Polarity of the resonant current (Note: this signal has a 1us blanking time during dead time. IPolarity signal listed here is after blanking. See ISNS section for details.)
SlewDone_H I Primary side switch node completes slewing from low to high
SlewDone_L I Primary side switch node completes slewing from high to low
VcrHigherThanVthh I VCR voltage is higher than the high threshold Vthh
VcrLowerThanVthl I VCR voltage is lower than the low threshold Vthl
VcrHighThanVcm I VCR voltage is high than the common mode voltage Vcm
WaveGenEn I Waveform generator enable
ZCS O Zero current switching is detected
HSON O High side gate driver on
LSON O Low side gate driver on
HSRampOn O High side compensation current ramp on
LSRampOn O Low side compensation current ramp on

The state machine is shown in Figure 42 and the description of the states and state transition conditions are in Table 5.

UCC256303 sluscu6_waveform_generator_state_ma.gifFigure 42. Waveform Generator State Machine

Table 5. States in Waveform Generator State Machine

STATE OUTPUT STATUS DESCRIPTION
IDLE HSON = 0
LSON = 0
HSRampOn = 0
LSRampOn = 0
ZCS = 0 		Both high side and low side are off in this state. Various circuits are operating in low power mode. This is the first state after POR. During burst off period, the system is in IDLE state as well. Upon entering IDLE state, load burst cycle counter, switching cycle counter, OCP1 counter, and OVP counter. Load startup cycle counter if WaveGenEn_Rising = 1
WakeUp HSON = 0
LSON = 0
HSRampOn = 0
LSRampOn = 0
ZCS = 0 		In this state, internal circuits wake up from low power mode.
LSON HSON = 0
LSON = 1
HSRampOn = 0
LSRampOn = 1
ZCS = 0 or 1 		In this state, the low side gate turns on; the low side ramp current source turns on. ZCS may be 0 or 1 depends on the detected result. More details will be described in ZCS section. Enable low side on timer.
DTLH HSON = 0
LSON = 0
HSRampOn = 1
LSRampOn = 0
ZCS = 0 or 1 		Dead time from low side on to high side on. Low side ramp current source turns off. High side ramp current source turns on. Enable dead time timer.
HSON HSON = 1
LSON = 0
HSRampOn = 1
LSRampOn = 0
ZCS = 0 or 1 		In this state, the high side gate turns on; the high side ramp current source turns on. ZCS may be 0 or 1 depends on the detected result. More details will be described in ZCS section. Enable high side on timer.
DTHL HSON = 0
LSON = 0
HSRampOn = 0
LSRampOn = 1
ZCS = 0 or 1 		Dead time from high side on to low side on. High side ramp current source turns off. Low side ramp current source turns on. Enable dead time timer.

Table 6. Waveform Generator State Machine State Transition Conditions

STATE TRANSITION CONDITION DESCRIPTION
1 WaveGenEn = 1 and FBLessThanBMT = 0 and minimum IDLE time expired
2 Wake up time expired
3 (VcrLowerThanVthl = 1 or LSON max timer expired) and LSON min timer expired
4 StartUpCounterExpired = 0 and DTStartUpTimerExpired = 1
DTMaxTimerExpired = 1
SlewDone_H = 1
SlewDone_H = 1 and MeasuredDTExpired = 1; (Note: this condition and the condition above is selectable using a trim bit, depending on whether dead time measure and match feature is wanted)
IPolarityFallingEdgeDetected = 1
5 (VcrHigherThanVthh = 1 or HSON max timer expired) and HSON min timer expired
6 StartUpCounterExpired = 0 and DTStartUpTimerExpired = 1
DTMaxTimerExpired = 1
SlewDone_L = 1
IPolarityFallingEdgeDetected = 1
7 WaveGenEn = 0
8 WaveGenEn = 0
(VcrLowerThanVthl = 1 or LSON max timer expired) and LSON min timer expired and (OCP1 counter expire or OVP counter expire)
9 WaveGenEn = 0
10 WaveGenEn = 0
BurstModeCountExpire = 1 and VcrHigherThanVcm = 1 and FBLessThanBMT = 1 and HSON min time expired
11 WaveGenEn = 0

Table 7. Waveform Generator State Machine Internal Counters and Timers

INTERNAL VARIABLE DESCRIPTION
Switching cycle counter This counter counts the switching cycle
OVP counter Bias Winding Overvoltage counter. The counter decrements every time a Bias Winding Overvoltage occurs
Startup counter Startup Counter. Counter gets set to 15 when wave generator enable toggles from low to high, and then decrements every switching cycle. When the count hits 0, the dead time state is no longer permitted to be exited via the startup dead time expiration.
Burst cycle counter Burst counter. Counter gets set to 15 and then decrements every switching cycle until it hits ‘0’. If FBLessThanBMT = 1 when the counter is ‘0’, the switcher will stop until FBLessThanBMT = 0.
OCP1 counter OCP1 counter. Counter gets set to 4 and then decrements every switching cycle when OCP1 occurs, until it hits ‘0’
Wakeup timer Wakeup state timer
DT max timer Maximum dead time timer
Startup dead time max timer Dead time max clamp for the first few start up cycles before the startup counter expires
Gate on min timer Minimum gate on time timer
Gate on max timer Maximum gate on time timer