SLUSAD7B April   2011  – July 2016 UCC25710

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multi-transformer Architecture
      2. 8.3.2 Start-Up and Non-Dimming Operation
      3. 8.3.3 Dimming Operation
      4. 8.3.4 Fault Condition Operation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Determining Transformer and Resonant Circuit Parameters
        2. 9.2.2.2  CS (Output Current Sense)
        3. 9.2.2.3  ICOMP (Current Amplifier Compensation)
        4. 9.2.2.4  SS (Soft Start)
        5. 9.2.2.5  FMAX (Maximum VCO Frequency)
        6. 9.2.2.6  FMIN (Minimum VCO Frequency)
        7. 9.2.2.7  GD1 and GD2 (Gate Drive 1 and 2)
        8. 9.2.2.8  LEDSW (LED Switch Drive)
        9. 9.2.2.9  DSR (Dimming Slew Rate)
        10. 9.2.2.10 DTY (Dimming Duty-Cycle Average)
        11. 9.2.2.11 DADJ (Dimming Duty-Cycle Adjust)
        12. 9.2.2.12 OV (Output Overvoltage)
        13. 9.2.2.13 UV (Output Undervoltage)
        14. 9.2.2.14 CL (Current Limit)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DW Package
20-Pin SOIC
Top View
UCC25710 pinout_lusad7.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 VCC P Connect a DC power voltage to VCC. Bypass VCC to GND with a 0.47-µF or larger ceramic capacitor using short PC-board traces. VCC directly supplies power to the gate drivers and VREF which biases all circuit blocks in the UCC25710. Undervoltage lockout (UVLO) comparator prevents operation until VCC rises above VVCCON.
2, 3 GD1&2 O Gate drive outputs operate 180° out of phase with a fixed 500 ns of dead time. They typically drive either primary end of a gate drive transformer. At start-up or during a fault recovery, initiating the LLC converter begins with GD2 turning on first.
4 GND P The ground pin is both the reference pin for the controller and the low-side return for the gate drive signals. Take special care to return all AC decoupling as close as possible to this pin and avoid any common trace length with analog signal return paths.
5 VREF O The internal 5-V supply and reference rail is brought out to this pin. A small decoupling capacitor to ground of 1 µF is required. VREF can support up to 10-mA current external to the device. VREF is enabled when VCC is above VVCCON and BLON is above VBLON.
6 LEDSW O The LED switch output is a control signal to a series LED switch. This output is low during a low level at the DIM input and whenever the LLC converter is disabled. PWM dimming is disabled during soft start, and the LEDSW output is high independent of the DIM input. A simple gate drive circuit is generally required at this output to drive the external FET.
7 DTY I/O The duty-cycle pin is averaged with a capacitor to ground to form a 1-D proportional voltage that is compared to the DADJ saw tooth voltage. The average voltage at this pin is 2.5 V(1-D)+0.1 V, where D is the dimming PWM duty-cycle the DIM input.
8 DADJ I/O A capacitor to ground at the duty-cycle adjust input sets the positive slope of a saw tooth waveform that is compared to a voltage proportional to 1-D where D is the dimming PWM duty-cycle of the DIM input. At the falling edge of the DIM input this comparison is used to extend the LLC ON-time beyond the ON-time of the LED series switch.
9 DIM I A PWM input signal at the dimming pin controls the average load current by cycling on and off both an external series LED switch and the gate drives to the LLC converter. A high on this pin corresponds to an ON condition. The controller ignores a low condition at this input during start-up or fault recovery until after the completion of a soft-start sequence.
10 BLON I Backlight ON is an enable signal for the control device. The signal is active high with a threshold of approx 1.2 V. The 5-V reference (VREF) is enabled with BLON which is the bias supply for many of the internal blocks of the device.
11 UV I This pin is used to monitor for an undervoltage condition on the load. A level below VUVTH on this pin causes the converter to disable the gate drive outputs as well as the LEDSW output. Immediately, a TRSTDLY (10 ms) reset delay and soft-start sequence is initiated. The reset delay and soft-start sequence is repeated as long at the UV pin is low at the end of the sequence.
12 OV I This pin is used to monitor for an overvoltage condition on an LED string. A level above VOVTH on this pin causes the converter to disable the gate drive outputs as well as the LEDSW output. If the OV input falls below its trip threshold the converter responds with a TRSTDLY (10 ms) reset delay and soft start.
13 CL I Current limit input connects to a signal that represents the power converter’s input current. Dual thresholds provide a shutdown retry or latch-off response.
14 DSR I/O The dimming slew rate pin is used to limit the rate of the VCO frequency change at the LLC on or off edges of a dimming PWM cycle. A capacitor to ground at this pin programs the maximum positive and negative slew rates that appear at the control input to the VCO. Pulling this pin below about 0.8 V disables the GD outputs.
15 CREF I Current Reference is used to set the regulating voltage for the LED current feedback signal at the CS input. This voltage input is set using a resistor divider from VREF. A nominal level of around 0.7 V is recommended although a range of 0.6 V to 2.7 V is accommodated. Internal reference levels of 0.5 V and 2.8 V replace the CREF input voltage at the current amplifier when the CREF pin voltage is respectively below or above these levels. The 0.5-V internal reference can be achieved by shorting CREF to ground, the internal 2.8-V reference can be achieved by shorting CREF to VREF.
16 CS I Current sense input monitors the LED current. This signal is compared to VCREF by the current amplifier to regulate the total LED current.
17 ICOMP O This output pin is used to compensate the current regulating loop. A capacitor, or capacitor resistor series combination is typically used. During current regulation the voltage into the VCO is slaved to this pin. Pulling this pin below about 0.8 V disables the GD outputs. During PWM dimming OFF-time this pin is tri-stated and the compensation network is meant to hold the proper LLC control voltage until the LLC converter is turned back on. To optimize this operation any DC loading on this pin must be avoided.
18 SS I/O The soft-start pin is used to control the rate of change of the VCO frequency during start-up. At start-up a low value pullup current source, ISS, is applied to this pin. A soft-start sequence is initiated at start-up and during any fault recovery. The SS pin must charge to 4.2 V before the controller allows PWM dimming to take place.
19 FMAX I/O The maximum frequency of the LLC converter is set by a resistor to ground at this pin. It is actually the difference between the maximum and minimum frequency that is set by this resistor.
20 FMIN I/O The minimum frequency of the LLC converter is set by a resistor to ground at this pin.