SLUSDX3C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

  • The most important layout guideline is to minimize the VCC-GND-bypass capacitor loop. Because this loop carries all the switching current, it is important to have a low ESL bypass capacitor between VCC and GND, with the minimum loop. Refer to Layout Example for how to layout the bypass capacitor on VCC to GND.
  • Return all control signals to GND pin through a separated plane. Avoid sharing path between the signal ground and the power ground. Use a short trace to connect GND pin to the thermal pad.
  • Separate the power stage components and signal component to minimize the coupling between these components
  • Short VREG-GND-decoupling capacitor loop is recommended. A low ESL decoupling capacitor between VREG and GND is needed to ensure stable operation of the internal linear regulator.
  • Add decoupling capacitors on RT and DT/OC pin to improve the noise immunity if it is needed. Refer to Section 7.3 for recommended maximum capacitor values.
  • Short SYNC pin to GND when external synchronization is not used.
  • Minimize the current loop with high di/dt and minimize the copper area of the switch-node with high dv/dt.
  • Other general power supply design layout guidelines.
  • The secondary side of the LLC converter is often connected with the high dv/dt node in the end equipment. In these cases, it is recommended to minimize the secondary-side copper area.