SLUSE23B March   2020  – May 2022 UCC27284-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stage
      3. 7.3.3 Level Shifter
      4. 7.3.4 Output Stage
      5. 7.3.5 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 Estimate Driver Power Losses
        3. 8.2.2.3 Selecting External Gate Resistor
        4. 8.2.2.4 Delays and Pulse Width
        5. 8.2.2.5 External Bootstrap Diode
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2 Estimate Driver Power Losses

The total power loss in gate driver device such as the UCC27284-Q1 is the summation of the power loss in different functional blocks of the gate driver device. These power loss components are explained in this section.

  1. Equation 4 describes how quiescent currents (IDD and IHB) affect the static power losses, PQC.
    Equation 4. GUID-D53A776B-B0FD-4CB1-8EB6-920C82B9E26E-low.gif

    it is not shown here, but for better approximation, add no load operating current, IDDO and IHBO in above equation.

  2. Equation 5 shows how high-side to low-side leakage current (IHBS) affects level-shifter losses (PIHBS).
    Equation 5. GUID-411F2B77-7B71-479C-918E-3DD3AF1920F0-low.gif

    where

    • D is the high-side MOSFET duty cycle
    • VHB is the sum of input voltage and voltage across bootstrap capacitor.
  3. Equation 6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG.
    Equation 6. GUID-EF172B22-D4E5-4087-ACB1-2A8D8750C32B-low.gif

    where

    • QG is the total MOSFET gate charge
    • fSW is the switching frequency
    • RGD_R is the average value of pullup and pulldown resistor
    • RGATE is the external gate drive resistor
    • RGFET(int) is the power MOSFETs internal gate resistor

    Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull down resistance of the driver output section is approximately 4 Ω. Substitute the application values to calculate the dynamic loss due to gate charge, which is 160 mW here.

  4. Equation 7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses, (PLS) during high-side switching.
    Equation 7. GUID-9B7A76A0-ACE1-4DCC-AE49-34902D19B120-low.gif

    For this example and simplicity, it is assumed that value of parasitic charge QP is 1 nC. Substituting values results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.

The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward conduction loss is computed as product of average forward voltage drop and average forward current.

Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.

Equation 8. GUID-0C4223B5-5156-4CFE-9F76-44B33C32E991-low.gif

where

  • PMAX is the maximum allowed power dissipation in the gate driver device
  • TJ is the recommended maximum operating junction temperature
  • TA is the ambient temperature of the gate driver device
  • RθJA is the junction-to-ambient thermal resistance

To better estimate the junction temperature of the gate driver device in the application, it is recommended to first accurately measure the case temperature and then determine the power dissipation in a given application. Then use ψJT to calculate junction temperature. After estimating junction temperature and measuring ambient temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an external gate resistor or power MOSFET) change during the development of the project, use θJA(effective) to estimate how these changes affect junction temperature of the gate driver device.

For detailed information regarding the thermal information table, please refer to the Semiconductor and Device Package Thermal Metrics application report.