SLUSDU4A December   2020  – May 2022 UCC27289

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Input Stages
      4. 7.3.4 Level Shifter
      5. 7.3.5 Output Stage
      6. 7.3.6 Negative Voltage Transients
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and VDD Capacitor
        2. 8.2.2.2 External Bootstrap Diode and Series Resistor
        3. 8.2.2.3 Estimate Driver Power Losses
        4. 8.2.2.4 Selecting External Gate Resistor
        5. 8.2.2.5 Delays and Pulse Width
        6. 8.2.2.6 VDD and Input Filter
        7. 8.2.2.7 Transient Protection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Curves

To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be as fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the UCC27289 is designed with high drive current capability and low resistance of the output stages. One of the common way to test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of the outputs would provide idea of drive capability of the gate driver device. There should not be any resistance in series with the load capacitor if large capacitor is used to measure the drive strength. Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This method is also useful in comparing performance of two or more gate driver devices.

UCC27289 was tested in application like environment. Synchrounous buck converter at no load was used to gnerate following waveforms. Switching frequency was set to 100kHz and input voltage was set to 100V. UCC27289 was driving BSC16DN250NS3 with 2 Ohm external resistor. All the waveforms were taken using single ended probes. Figure 8-3 and Figure 8-4 shows rise time and fall time of HO respectively. Figure 8-5 and Figure 8-6 shows rise time and fall time of LO respectively. Internal bootstrap diode and external bootstrap capacitor generated the high-side bias.

As explained in Section 8.2.2.5, propagation delay plays an important role in reliable operation of many applications. Figure 8-7 and Figure 8-8 shows LO rise and fall propagation delay of UCC27289. Similar propagation delay was observed for HO output as well.

GUID-CCD21BD5-7FB0-4FE7-8248-E89411760B68-low.gif
VDD=12 V, HS=100V
Figure 8-3 HO Rise Time
GUID-F230A920-6789-4FD9-8F21-770D53A7FC81-low.gif
VDD=12V, HS=100V
Figure 8-5 LO Rise Time
GUID-0B034E40-1F38-4852-A325-7266D46369DC-low.gif
VDD=12 V
Figure 8-7 Turn-on Propagation Delay
GUID-D150373C-0D83-4488-BB6C-2537910C5B12-low.gif
VDD=10V, Vin=100VCL=1nFCh1=HI Ch2=LI Ch3=HO Ch4=LO
Figure 8-9 Input Negative Voltage
GUID-F230A920-6789-4FD9-8F21-770D53A7FC81-low.gif
VDD==12 V, HS=100V
Figure 8-4 HO Fall Time
GUID-F41377F2-930B-4892-A2C9-3117C70FF979-low.gif
VDD=12V, HS=100V
Figure 8-6 LO Fall Time
GUID-F911B352-B50F-479E-8462-190316B7C6AA-low.gif
VDD=12 V
Figure 8-8 Turn-off Propagation Delay