SLUSEX3C April   2023  – July 2024 UCC27301A-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Boot Diode
      6. 6.3.6 Output Stages
      7. 6.3.7 Negative Voltage Transients
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Threshold Type
        2. 7.2.2.2 VDD Bias Supply Voltage
        3. 7.2.2.3 Peak Source and Sink Currents
        4. 7.2.2.4 Propagation Delay
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

UCC27301A-Q1 DDA Package 8-Pin SOIC with PowerPad™ Top ViewFigure 4-1 DDA Package 8-Pin SOIC with PowerPad™ Top View
UCC27301A-Q1 DRC Package 10-Pin SON Top ViewFigure 4-2 DRC Package 10-Pin SON Top View
Table 4-1 Pin Functions
PIN TYPE(3) DESCRIPTION
NAME DDA DRC
EN N/A 6 I Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will disable the driver. A filter capacitor, typically 1-10nF, is recommended to be placed from EN to VSS to increase noise immunity in sensitive applications.
HB 2 3 P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022µF to 0.1µF. The capacitor value is dependant on the gate charge of the high-side MOSFET and must also be selected based on speed and ripple criteria.
HI 5 7 I High-side input.(1)
HO 3 4 O High-side output. Connect to the gate of the high-side power MOSFET.
HS 4 5 P High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin.
LI 6 8 I Low-side input.(1)
LO 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
VDD 1 1 P Positive supply to the lower-gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor range is 0.22µF to 4.7µF (see (2)).
VSS 7 9 G Negative supply terminal for the device that is generally grounded.
Thermal pad(4) Pad Pad — Connect to a large thermal mass trace and GND plane to dramatically improve thermal performance.
(1) HI, LI, and EN inputs are assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100Ω. If the source impedance is greater than 100Ω, add a bypassing capacitor, each, between HI to VSS, LI to VSS, and EN to VSS. The added capacitor value depends on the noise levels presented on the pins, typically from 1nF to 10nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs.
(2) For cold temperature applications TI recommends the upper capacitance range. Follow the Layout Guidelines for PCB layout.
(3) G = Ground, I = Input, O = Output, and P = Power.
(4) Pin VSS and the exposed thermal pad are internally connected on the DRC package only. On the DDA package, the thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the substrate which is the ground of the device.