SLUSEY5 July   2024 UCC27301A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Boot Diode
      6. 6.3.6 Output Stages
      7. 6.3.7 Negative Voltage Transients
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Threshold Type
        2. 7.2.2.2 VDD Bias Supply Voltage
        3. 7.2.2.3 Peak Source and Sink Currents
        4. 7.2.2.4 Propagation Delay
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information
    3. 12.3 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DRC|10
Thermal pad, mechanical data (Package|Pins)

5.5 Electrical Characteristics

VDD = VHB =12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to +150°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current VLI = VHI = 0 V, VEN = 3V 0.11 0.19 mA
IDDO VDD operating current  f = 500 kHz, CLOAD = 0, VEN = 3V 1.4 3 mA
IHB Boot voltage quiescent current VLI = VHI = 0 V, VEN = 3V 0.065 0.12 mA
IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0, VEN = 3V 1.3 3 mA
IHBS HB to VSS quiescent current VHS = VHB = 105 V, VEN = 3V 0.0005 1 μA
IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0, VEN = 3V 0.03 1 mA
IDD_DIS Driver Current when EN pin is pulled low (Disabled) DRC package only, VEN = 0 3 μA
INPUT
VHIT_HI Input voltage high threshold  1.7 2.3 2.55 V
VHIT_LI Input voltage high threshold  1.7 2.3 2.55 V
VLIT_HI Input voltage low threshold  1.2 1.6 1.9 V
VLIT_LI Input voltage low threshold  1.2 1.6 1.9 V
VIHYS  HI Input voltage Hysteresis 0.7 V
VIHYS  LI Input voltage Hysteresis  0.7 V
RIN_HI Input pulldown resistance  VIN = 3V 68 kΩ
RIN_LI Input pulldown resistance  VIN = 3V 68 kΩ
ENABLE
VEN Voltage threshold on EN pin to enable the driver DRC package only 1.7 2.3 2.55 V
VDIS Voltage threshold on EN pin to disable the driver DRC package only 1.2 1.6 1.9 V
VENHYS Enable pin Hysteresis DRC package only 0.7 V
REN EN pin internal pull-down resistance DRC package only, VEN = 3V 80 kΩ
TEN Time to enable the driver once the EN pin is pulled high DRC package only, VEN = 3V 10 μs
TDIS Time to disable the driver once the EN pin is pulled low DRC package only, VEN = 0V 0.1 μs
UNDERVOLTAGE PROTECTION (UVLO)
VDDR VDD rising threshold 6.2 7 7.8 V
VDDHYS VDD threshold hysteresis 0.5 V
VHBR VHB rising threshold 5.6 6.7 7.9 V
VHBHYS VHB threshold hysteresis 1.1 V
BOOTSTRAP DIODE
VF Low-current forward voltage I VDD - HB = 100 μA 0.65 0.85 V
VFI High-current forward voltage I VDD - HB = 100 mA 0.9 1.05 V
RD Dynamic resistance, ΔVF/ΔI I VDD - HB = 160 mA and 180 mA 0.3 0.55 0.85 Ω
LO GATE DRIVER
VLOL Low level output voltage ILO = 100 mA 0.07 0.19 V
VLOH High level output voltage ILO = -100 mA, VLOH = VDD – VLO 0.11 0.29 V
Peak pullup current(1) VLO = 0 V 3.7 A
Peak pulldown current(1) VLO = 12 V 4.5 A
HO GATE DRIVER
VHOL Low level output voltage IHO = 100 mA 0.07 0.19 V
VHOH High level output voltage IHO = –100 mA, VHOH = VHB- VHO 0.11 0.29 V
Peak pullup current(1) VHO = 0 V 3.7 A
Peak pulldown current(1) VHO = 12 V 4.5 A
(1) Parameter not tested in production.