SLUSEY2B June   2023  – July 2024 UCC27311A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages
      2. 6.3.2 Enable
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Boot Diode
      6. 6.3.6 Output Stages
      7. 6.3.7 Negative Voltage Transients
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Threshold Type
        2. 7.2.2.2 VDD Bias Supply Voltage
        3. 7.2.2.3 Peak Source and Sink Currents
        4. 7.2.2.4 Propagation Delay
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Overview

The UCC27311A-Q1 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel MOSFETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long as the signals meet the turn-on and turn-off threshold specifications of the device. The floating high-side driver is capable of operating with an HB voltage up to 115V with respect to VSS. A 120V bootstrap diode is integrated in the UCC27311A-Q1 device to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and provides clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is provided (in DRC packaged parts) to enable or disable the driver.

In the UCC27311A-Q1 device, the high side and low side have seperate inputs that allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27311A-Q1.The high-side driver is referenced to the switch node (HS), which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which is typically ground. The UCC27311A-Q1 functions are divided into the input stages, UVLO protection, level shift, boot diode, and output driver stages.

Table 6-1 UCC27311A-Q1 Highlights
FEATUREBENEFIT
3.7A source and 4.5A sink currentHigh peak current ideal for driving large power MOSFETs with minimal power loss (fast-drive capability at Miller plateau)
Input pins (HI and LI) can directly handle –10VDC up to 20VDCIncreased robustness and ability to handle undershoot and overshoot can interface directly to gate-drive transformers without having to use rectification diodes
120V internal boot diodeProvides voltage margin to meet surge requirements
Switch node (HS pin) able to handle –(28–VDD)V absolute maximum for 100nsAllows the high-side channel to have extra protection from inherent negative voltages caused by parasitic inductance and stray capacitance
Robust ESD circuitry to handle voltage spikesExcellent immunity to large dV/dT conditions
20ns propagation delay with 7.2ns rise time and 5.5ns fall timeBest-in-class switching characteristics and extremely low-pulse transmission distortion
Enable/disable functionalityOffers additional control over the driver for different system states (such as powerup sequencing) and a low quiescent current consumption when disabled
4ns (typical) delay matching between channelsAvoids transformer volt-second offset in bridge
TTL optimized thresholds with increased hysteresisComplementary to analog or digital PWM controllers; increased hysteresis offers added noise immunity