SLUS504I September   2002  – November 2023 UCC27321 , UCC27322 , UCC37321 , UCC37322

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Power Dissipation Ratings
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Source and Sink Capabilities during Miller Plateau
      4. 8.3.4 Enable
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Configuration
        2. 9.2.2.2 Input Threshold Type
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Peak Source and Sink Currents
        5. 9.2.2.5 Enable and Disable Function
        6. 9.2.2.6 Propagation Delay
        7. 9.2.2.7 Power Dissipation
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
    1.     40
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Revision History

Changes from Revision H (January 2016) to Revision I (November 2023)

  • Deleted P package from Device Information tableGo
  • Deleted P package from Description (continued) sectionGo
  • Deleted P package from Pin Configuration and Functions sectionGo
  • Changed ESD Ratings from ±2500 V and ±1500 V to ±2000 V and ±1000 VGo
  • Changed input threshold voltage values, deleted VOH output high level and VOL output low level, changed output resistance high and output resistance low values and deleted Latch-up protection from Electrical Characteristics.Go
  • Deleted P package data from Power Dissipations Ratings sectionGo
  • Changed Figure 7-16 Go

Changes from Revision G (May 2013) to Revision H (January 2016)

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

Changes from Revision F (March 2012) to Revision G (May 2013)

  • Updated AGND pin description. Go
  • Changed minimum value for input voltage from –5 to –0.3 V in the Absolute Maximum Ratings table.Go
  • Added CLOAD = 10 nF to Fall Time vs Supply Voltage graphGo
  • Changed Changed x-axis values from 1, 10, 100 to 0.1, 1, 10 in Rise Time vs Load Capacitance graphGo
  • Changed Changed x-axis values from 1, 10, 100 to 0.1, 1, 10 in Fall Time vs Output Capacitance graphGo