SLUS678D March   2008  – November 2023 UCC27324-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Overall Electrical Characteristics
    6. 5.6  Power Dissipation Characteristics
    7. 5.7  Input (INA, INB) Electrical Characteristics
    8. 5.8  Output (OUTA, OUTB) Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Output Stage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Parallel Outputs
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Propagation Delay
        2. 7.2.2.2 Source and Sink Capabilities During Miller Plateau
        3. 7.2.2.3 Supply Voltage (VDD)
        4. 7.2.2.4 Drive Current and Power Requirements
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Layout Guidelines

For the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-μF) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low-impedance characteristic for the expected current levels in the driver application.

In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high Δi/Δt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is advantageous to connect the driver as close as possible to the leads. The driver layout has ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections also should be made with a small enclosed loop area to minimize the inductance.

PCB layout is a critical step in the production process in high-current fast-switching circuits to ensure appropriate operation and design robustness. The UCC27324-Q1 MOSFET driver is capable of delivering large current peaks with rapid rise and fall times at the gate of a power MOSFET to facilitate voltage transitions quickly. At higher VDD voltages, the peak current capability is even higher. High di/dt causes unacceptable ringing if the trace lengths and impedances are not well controlled.

  • Locate the driver device as close as possible to the power device in order to minimize the length of high-current traces between the output pins and the gate of the MOSFET being driven.
  • Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace length to improve the noise filtering. Place these capacitors as close to each other as is allowed, as shown by C1 and C2 in Figure 9-1 which ensures minimal trace inductance and gives the effect of a capacitor bank. These capacitors support high peak current being drawn from VDD during turn-on of the power MOSFET. The use of low inductance surface mount components is highly recommended.
  • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver is connected the other circuit nodes such as the source of the power MOSFET and ground of the PWM controller at one single point. The connected paths must be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
  • Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead, the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help with thermal protection.
  • Tie pins 1 and 8 to GND to eliminate any chance of noise causing malfunction on a floating node.