SLUSEW3 October   2023 UCC27332-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Power On Reset
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
    4. 7.4 Device Functional Modes
  9. 8  Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Driving MOSFET
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input-to-Output Configuration
          2. 8.2.1.2.2 Input Threshold Type
          3. 8.2.1.2.3 VDD Bias Supply Voltage
          4. 8.2.1.2.4 Peak Source and Sink Currents
          5. 8.2.1.2.5 Enable and Disable Function
          6. 8.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 8.2.1.2.7 Power Dissipation
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Consideration
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise noted, VDD = 4.5 V to 18 V, TA = TJ = –40°C to 125°C, 1-µF capacitor from VDD to GND, No load on the output. Typical condition specifications are at 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS CURRENTS
IVDD VDD static supply current VIN = 3.3V, EN = VDD 150 380 uA
IVDD VDD static supply current VIN = 0 V, EN = VDD

107

180

 uA
IVDDO VDD dynamic operating current CLOAD = 1.8 nF, fSW = 100 kHz, EN = VDD, VIN = 0 V to 3.3 V PWM 3.9 4.5 mA
IDIS VDD disable current VIN = 3.3 V, EN = 0 V 280 380 uA
POWER ON RESET (POR)
VVDD_ON VDD POR rising threshold 2.1 3.0 4.0 V
VVDD_OFF VDD POR falling threshold 1.8 2.7 3.5 V
VVDD_HYS VDD POR hysteresis 0.3 V
INPUT (IN)
VIN_H Input signal high threshold, Output High, EN=HIGH 1.6 2.2 2.5 V
VIN_L Input signal low threshold Output Low, EN=HIGH 0.8 1.2 1.5 V
VIN_HYS Input signal hysteresis 1.0 V
ENABLE (EN)
VEN_H Enable signal high threshold Output high, IN=HIGH 1.7 2.3 2.7 V
VEN_L Enable signal low threshold Output low, IN=HIGH 1.1 1.8 2.0 V
VEN_HYS Enable signal hysteresis 0.7 V
REN EN pin pullup resistance EN = 0 V 100 kΩ
OUTPUT (OUT)
ISRC(1) Peak output source current VDD = 14V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz 9 A
ISNK(1) Peak output sink current VDD = 14V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz –9 A
ROH(2) OUTH, pullup resistance IOUT = –10 mA

See: Section 7.3.4

 0.6 1.5 Ω
ROL OUTL, pulldown resistance IOUT = 10 mA 0.4 1 Ω
(1) Parameter not tested in production.
(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.