SGLS274I September 2008 – November 2023 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1
PRODUCTION DATA
The UCC2742x-Q1 family of devices are high-speed dual MOSFET drivers capable of delivering large peak currents into capacitive loads. Two standard logic options are offered: dual inverting and dual noninverting drivers. They are offered in the standard 8-pin SOIC (D) package. The thermally enhanced 8-pin PowerPAD Package MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability.
Using a design that inherently minimizes shoot-through current, these drivers deliver 4-A current where it is needed most, at the Miller plateau region, during the MOSFET switching transition. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.
The UCC2742x-Q1 provide enable (ENBL) functions to have better control of the operation of the driver applications. ENBA and ENBB are implemented on pins 1 and 8, which were previously left unused in the industry standard pinout. They are internally pulled up to VDD for active-high logic and can be left open for standard operation.
PART NUMBER(1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC2742x-Q1 | SOIC (8) | 4.90 mm × 3.91 mm |
MSOP With PowerPAD (8) | 3.00 mm × 3.00 mm |
ORDERABLE PART NUMBER(1) | CONFIGURATION |
---|---|
UCC27423QDGNRQ1 | Dual Inverting |
UCC27424QDGNRQ1 | Dual Noninverting |
UCC27423QDRQ1 | Dual Inverting |
UCC27424QDRQ1 | Dual Noninverting |
UCC27425QDRQ1 | One Inverting, One Noninverting |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | ENBA | I | Enable input for the driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state. |
2 | INA | I | Input A. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating. |
3 | GND | — | Common ground. This ground must be connected very closely to the source of the power MOSFET which the driver is driving. |
4 | INB | I | Input B. Input signal of the B driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating. |
5 | OUTB | O | Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. |
6 | VDD | — | Supply voltage and the power input connection for this device. |
7 | OUTA | O | Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. |
8 | ENBB | I | Enable input for the driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDD | Supply voltage | –0.3 | 16 | V | |
IOUT | Output current | DC | 0.3 | A | |
Pulsed, 0.5 µs | 4.5 | ||||
VIN | Input voltage | INA, INB | –5 | 6(3) or (VDD + 0.3)(3) | V |
VEN | Enable voltage | ENBA, ENBB | –0.3 | 6(3) or (VDD + 0.3)(3) | V |
PD | Power dissipation | TA = 25°C (D package) | 650 | mW | |
TA = 25°C (DGN package) | 3 | W | |||
TJ | Junction operating temperature | –55 | 150 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |