SLUSET2A may   2022  – july 2023 UCC27444-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Supply Current
      2. 7.3.2 Input Stage
      3. 7.3.3 Enable Function
      4. 7.3.4 Output Stage
      5. 7.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD and Power On Reset
        2. 8.2.2.2 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

Unless otherwise noted, VDD = VEN = 4.5 V to 18 V, TA = TJ = –40°C to 125°C, 1-µF capacitor from VDD to GND, no load on the output. Typical condition specifications are at 25°C (1).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRxRise timeCLOAD = 1.8 nF, 10% to 90%, Vin = 0 V – 5 V

11

25ns
tFxFall timeCLOAD = 1.8 nF, 90% to 10%, Vin = 0 V – 5V723ns
tD1xTurn-on propagation delayCLOAD = 1.8 nF, VINx_H of the input rise to 10% of output rise, Vin = 0 V –5 V, Fsw = 500 kHz, 50% duty cycle1833ns
tD2xTurn-off propagation delayCLOAD = 1.8 nF, VINx_L of the input fall to 90% of output fall, Vin = 0 V – 5 V, VDD= 5V -18V, Fsw = 500 kHz, 50% duty cycle3050ns
tD3xEnable propagation delayCLOAD = 1.8 nF, VENx_H of the enable rise to 10% of output rise, Vin = 0 V – 5 V, Fsw = 500 kHz, 50% duty cycle1931ns
tD4xDisable propagation delayCLOAD = 1.8 nF, VENx_L of the enable fall to 90% of output fall, Vin = 0 V – 5 V, Fsw = 500 kHz, 50% duty cycle2452ns
tMDelay matching between two channelsCLOAD = 1.8 nF, Vin = 0 V – 5 V, Fsw = 500 kHz, 50% duty cycle, INA = INB, |tRA – tRB|, |tFA – tFB|15ns
tPWminMinimum input pulse widthCL = 1.8 nF, Vin = 0 V – 5 V, Fsw = 500 kHz, Vo > 1.5 V822ns
(1) Switching parameters are not tested in production.