SLUSD95A
March 2018 β January 2024
UCC27511A
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Handling Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
VDD and Undervoltage Lockout
6.3.2
Operating Supply Current
6.3.3
Input Stage
6.3.4
Enable Function
6.3.5
Output Stage
6.3.6
Low Propagation Delays
6.4
Device Functional Modes
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input-to-Output Logic
7.2.2.2
Input Threshold Type
7.2.2.3
VDD Bias Supply Voltage
7.2.2.4
Peak Source and Sink Currents
7.2.2.5
Enable and Disable Function
7.2.2.6
Propagation Delay
7.2.2.7
Thermal Information
7.2.2.8
Power Dissipation
7.2.3
Application Curves
8
Power Supply Recommendations
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DBV|6
MPDS026Q
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slusd95a_oa
slusd95a_pm
1
Features
Input Pins Capable of Withstanding β5V Below GND pin
Low-Cost Gate-Driver Device Offering Superior Replacement of NPN and PNP Discrete Solutions
Strong Sink Current Offers Enhanced Immunity Against Miller Turnon
Split Output Configuration (Allows Easy and Independent Adjustment of Turnon and Turnoff Speeds)
Fast Propagation Delays (13ns typical)
Fast Rise and Fall Times (8ns and 7ns typical)
4.5V to 18V Single Supply Range
Outputs Held Low During V
DD
UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
TTL and CMOS Compatible Input-Logic Threshold (Independent of Supply Voltage)
Wide Hysteresis (1V typical)
for High-Noise Immunity
Dual-Input Design (Choice of an Inverting (INβ Pin) or Non-Inverting (IN+ Pin) Driver Configuration)
Unused Input Pin can be Used for Enable or Disable Function
Output Held Low when Input Pins are Floating
Input Pin Absolute Maximum Voltage Levels Not Restricted by V
DD
Pin Bias Supply Voltage