12.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device operation and design robustness. The UCC2751xA-Q1 gate driver incorporates short-propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current capability is even higher (4-A, 4-A peak current is at VDD = 12 V). Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers.

• Locate the driver device as close as possible to power device to minimize the length of high-current traces between the output pins and the gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support high-peak current being drawn from VDD during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip capacitors is highly recommended.
• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD bypass capacitor) should be minimized as much as possible to keep the stray inductance to a minimum. High dI/dt is established in these loops at two instances—during turnon and turnoff transients, which will induce significant voltage transients on the output pin of the driver device and gate of the power switch.
• Wherever possible parallel the source and return traces, taking advantage of flux cancellation.
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power switch and ground of PWM controller at one point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well.

12.2 Layout Example

Figure 26. Layout Example

12.3 Thermal Consideration

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the package. For a gate driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package are listed in the Thermal Information table. For detailed information regarding the thermal information table, please refer to the Application Note from Texas Instruments entitled Semiconductor and IC Package Thermal Metrics (SPRA953).

12.4 Power Dissipation

Power dissipation of the gate driver has two portions as shown in Equation 2:

Use Equation 3 to calculate the DC portion of the power dissipation.

The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through). The UCC2751xA-Q1 family of devices features very low quiescent currents (less than 1 mA, refer Figure 7) and contains internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of the P_DC on the total power dissipation within the gate driver can be assumed to be negligible.

The power dissipated in the gate-driver package during switching (P_SW) depends on the following factors:

• Gate charge required of the power device (usually a function of the drive voltage V_G, which is very close to input bias supply voltage VDD because of low V_OH drop-out).
• Switching frequency.
• Use of external gate resistors.

When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 4.

Equation 4.

where

• C_LOAD is load capacitor
• V_DD is bias voltage feeding the driver

There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss given by Equation 5.

Equation 5.

where

• f_SW is the switching frequency

The switching load presented by a power MOSFET or IGBT can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Q_G, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equation, Q_G = C_LOAD × V_DD, to provide the following equation for power:

Equation 6.

This power P_G is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET or IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculated as follows:

Equation 7.

where

• R_OFF = R_OL
• R_ON (effective resistance of pullup structure) = 1.4 × R_OL