SLVSDH6A
April 2017 – June 2024
UCC27524A1-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Description (continued)
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.6.1
Timing Diagrams
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Operating Supply Current
7.3.2
Input Stage
7.3.3
Enable Function
7.3.4
Output Stage
7.3.5
Low Propagation Delays and Tightly Matched Outputs
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
VDD and Undervoltage Lockout
8.2.2.2
Drive Current and Power Dissipation
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGN|8
MPDS046F
Thermal pad, mechanical data (Package|Pins)
DGN|8
PPTD362A
Orderable Information
slvsdh6a_oa
slvsdh6a_pm
1
Features
Qualified for automotive applications
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to +125°C ambient operating temperature range
Industry-standard pin out
Two independent gate-drive channels
5A peak source and sink-drive current
Independent enable function for each output
TTL and CMOS-compatible logic threshold independent of supply voltage
Hysteretic-logic thresholds for high-noise immunity
Ability to handle negative voltages (–5V) at inputs
Inputs and enable pin voltage levels not restricted by V
DD
pin bias supply voltage
4.5V to 18V single supply range
Outputs held low during V
DD
-UVLO, (ensures glitch-free operation at power up and power down)
Fast propagation delays (17ns typical)
Fast rise and fall times (3.5ns and 6ns typical)
1ns typical delay matching between two channels
Ability to parallel two outputs for high-drive current
Outputs held low when inputs are floating
MSOP-8
PowerPad™
package
Operating junction temperature range of –40°C to 150°C