SNVSA89A December   2014  – May 2015 UCC27528-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Undervoltage Lockout
      2. 8.3.2 Operating Supply Current
      3. 8.3.3 Input Stage
      4. 8.3.4 Enable Function
      5. 8.3.5 Output Stage
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Logic
        2. 9.2.2.2 Enable and Disable Function
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Drive Current and Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device operation and design robustness. The UCC27528-Q1 gate driver incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very-fast rise and fall times at the gate of the power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers:

  • Locate the driver device as close as possible to power device to minimize the length of high-current traces between the output pins and the gate of the power device.
  • Locate the VDD bypass capacitors between the VDD and GND pins as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support the high peak current that is drawn from the VDD pin during turn-on of power MOSFET. The use of low inductance SMD components, such as chip resistors and chip capacitors, is highly recommended.
  • The turn-on and turn-off current-loop paths (driver device, power MOSFET, and VDD bypass capacitor) should be minimized as much as possible to keep the stray inductance to a minimum. High dI/dt is established in these loops at two instances: during turn-on transients and turn-off transients, which will induce significant voltage transients on the output pin of the driver device and gate of the power MOSFET.
  • Wherever possible parallel the source and return traces, taking advantage of flux cancellation.
  • Separate power traces and signal traces, such as output and input signals.
  • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as the source of power MOSFET, the ground of PWM controller, and other sources at one, single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
  • Use a ground plane to provide noise shielding. Fast rise and fall times at the OUTx pin may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation.

11.2 Layout Example

UCC27528-Q1 layoutex_ssnvsa89.gifFigure 27. Layout Example for UCC27528-Q1

11.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a gate driver device to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits.