SLUSBD9A February   2013  – September 2024 UCC27532

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Feature Description
      1. 6.2.1 VDD Under Voltage Lockout
      2. 6.2.2 Input Stage
      3. 6.2.3 Enable Function
      4. 6.2.4 Output Stage
      5. 6.2.5 Power Dissipation
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
  9. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Electrical Characteristics

Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, IN switching from 0 V to VDD, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together. Typical condition specifications are at 25°C.
PARAMETERCONDITIONMINTYPMAXUNITS
Bias Currents
IDDoffStartup Current, VDD = 7.0IN, EN = VDD100240350μA
IN, EN = GND100250350
Under Voltage Lockout (UVLO)
VONSupply start threshold8.08.99.8V
VOFFMinimum operating voltage after supply start7.38.29.1
VDD_HSupply voltage hysteresis0.7
Input (IN)
VIN_HInput signal high thresholdVDD = 16V, Output high8.89.410V
VIN_LInput signal low thresholdVDD = 16V, Output low6.77.37.9
VIN_HYSInput signal hysteresisVDD = 16V2.1
Enable (EN)
VEN_HEnable signal high thresholdVDD = 16V, Output high1.71.92.1V
VEN_LEnable signal low thresholdVDD = 16V, Output low0.81.01.2
VEN_HYSEnable signal hysteresisVDD = 16V0.9
Outputs (OUTH/OUTL)
ISRC/SNKSource peak current (OUTH)/ sink peak current (OUTL)(13)(1)CLOAD = 0.22 µF, f = 1 kHz-2.5/+5A
VOHOUTH, high voltageIOUTH = -10 mAVDD -0.2VDD -0.12VDD -0.07V
VOLOUTL, low voltageIOUTL = 100 mA0.0650.125
ROHOUTH, pull-up resistance (15)(3)TA = 25°C, IOUT = -10 mA111212.5Ω
TA = -40°C to 140°C, IOUT = -10 mA71220
ROLOUTL, pull-down resistanceTA = 25°C, IOUT = 100 mA0.450.650.85
TA = -40°C to 140°C, IOUT = 100 mA0.30.651.25
Switching Time (1)(2)
tRRise timeCLOAD = 1.8 nF15ns
tFFall timeCLOAD = 1.8 nF7
tD1Turn-on propagation delayCLOAD = 1.8 nF, IN = 0 V to VDD1726
tD2Turn-off propagation delayCLOAD = 1.8 nF, IN = VDD to 0 V1726
(1) Ensured by design and tested during characterization. Not production tested.
(2) See Figure 5-1.
(3) Output pull-up resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure. The effective dynamic pull-up resistance is 3 x ROL.
UCC27532 Timing Diagram (OUTH tied to OUTL)(Input = IN, Output = OUT (EN = VDD), or Input = EN, Output = OUT (IN = VDD)Figure 5-1 Timing Diagram (OUTH tied to OUTL)(Input = IN, Output = OUT (EN = VDD), or Input = EN, Output = OUT (IN = VDD)