SLUSBD9A February   2013  – September 2024 UCC27532

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Feature Description
      1. 6.2.1 VDD Under Voltage Lockout
      2. 6.2.2 Input Stage
      3. 6.2.3 Enable Function
      4. 6.2.4 Output Stage
      5. 6.2.5 Power Dissipation
    3. 6.3 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
  9. Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Thermal Considerations
  10. Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VDD Under Voltage Lockout

The UCC27532 device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply circuit blocks. To ensure acceptable power dissipation in the power switch, this UVLO prevents the operation of the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than VON during power-up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si MOSFETs, IGBTs, and emerging SiC FETs.

UCC27532 Power UpFigure 6-1 Power Up