The UCC27611 is a single-channel, high-speed, gate driver optimized for 5-V drive, specifically addressing enhancement mode GaN FETs. The drive voltage VREF is precisely controlled by internal linear regulator to 5 V. The UCC27611 offers asymmetrical rail-to-rail peak current drive capability with 4-A source and 6-A sink. Split output configuration allows individual turnon and turnoff time optimization depending on FET. Package and pinout with minimum parasitic inductances reduce the rise and fall time and limit the ringing. Additionally, the short propagation delay with minimized tolerances and variations allows efficient operation at high frequencies. The 1-Ω and 0.35-Ω resistance boosts immunity to hard switching with high slew rate dV and dt.
The independence from VDD input signal thresholds ensure TTL and CMOS low-voltage logic compatibility. For safety reason, when the input pins are in a floating condition, the internal input pullup and pulldown resistors hold the output LOW. Internal circuitry on VREF pin provides an undervoltage lockout function that holds output LOW until VREF supply voltage is within operating range. UCC27611 is offered in a small 2.00 mm × 2.00 mm SON-6 package (DRV) with exposed thermal and ground pad that improves the package power-handling capability. The UCC27611 operates over wide temperature range from –40°C to 140°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC27611 | SON (6) | 2.00 mm × 2.00 mm |
Changes from E Revision (February 2018) to F Revision
Changes from D Revision (October 2017) to E Revision
Changes from C Revision (December 2015) to D Revision
Changes from B Revision (May 2013) to C Revision
Changes from A Revision (December 2012) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VDD | I | Bias supply input. Connect a ceramic capacitor minimum from this pin to the GND pin as close as possible to the device with the shortest trace lengths possible. |
2 | IN– | I | Inverting input. Pull IN+ to VDD to enable output, when using the driver device in Inverting configuration. |
3 | IN+ | I | Noninverting input. Pull IN– to GND to enable output, when using the driver device in noninverting configuration. |
4 | OUTL | O | 6-A sink current output of driver. |
5 | OUTH | O | 4-A source current output of driver. |
6 | VREF | O | Drive voltage, output of internal linear regulator. Connect a ceramic capacitor minimum from this pin to the GND pin as close as possible to the device with the shortest trace lengths possible. |
7 | GND PAD | — | Ground. All signals are referenced to this node. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage | –0.3 | 20 | V |
OUTH | –0.3 | VREF + 0.3 | V | |
OUTL | –0.3 | VREF + 0.3 | V | |
VREF | 6 | V | ||
IN+, IN– | –0.3 | 20 | V | |
Iout_DC | Continuous source current of OUTH/sink current of OUTL | 0.3 | 0.6 | A |
Iout_pulsed | Continuous source current of OUTH/sink current of OUTL (0.5 µs), | 4 | 6 | A |
Lead temperature, soldering, 10 sec. | 300 | °C | ||
Lead temperature, reflow | 260 | °C | ||
TJ | Operating virtual junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –65 | 150 | °C |