SLUSFL4A April   2024  – October 2024 UCC27614-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Undervoltage Lockout
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Input-to-Output Configuration
          2. 7.2.1.2.2 Input Threshold Type
          3. 7.2.1.2.3 VDD Bias Supply Voltage
          4. 7.2.1.2.4 Peak Source and Sink Currents
          5. 7.2.1.2.5 Enable and Disable Function
          6. 7.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
          7. 7.2.1.2.7 Power Dissipation
        3. 7.2.1.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Consideration
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DSG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

UCC27614-Q1 DSG Package 8-Pin SON Top View Figure 4-1 DSG Package 8-Pin SON Top View
UCC27614-Q1 D Package 8-Pin SOIC Top View Figure 4-2 D Package 8-Pin SOIC Top View
UCC27614-Q1 DGN Package 8-Pin VSSOP Top View Figure 4-3 DGN Package 8-Pin VSSOP Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME DSG NO. D DGN NO.
GND 2,3 4,5 G Device ground or reference
EN — 3 I Enable or disable control pin. If not used, connect to VDD.
IN — 2 I Non-inverting PWM input
IN+ 1 — I Non-inverting PWM input. If not used, connect to VDD.
IN- 8 — I Inverting PWM input. If not used, connect to GND.
OUT 4,5 6,7 O Output of the driver
VDD 6,7 1,8 P Driver bias supply. Connect the positive node of the voltage source to this pin through an impedance for high common mode noise rejection. Bypass this pin with two ceramic capacitors, generally >=1 µF and 0.1 µF, which are referenced to GND pin of this device.
Thermal Pad Thermal Pad(2) — Connect to GND through large copper plane.

This pad is not a low-impedance path to GND.
(1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection
(2) Applies to DGN package.