The UCC27624-Q1 is a dual-channel, high-speed, low-side gate driver that effectively drives MOSFET, IGBT, SiC, and GaN power switches. UCC27624-Q1 has a typical peak drive strength of 5A, which reduces rise and fall times of the power switches, lowers switching losses, and increases efficiency. The device's fast propagation delay (17ns typical) yields better power stage efficiency by improving the deadtime optimization, pulse width utilization, control loop response, and transient performance of the system.
UCC27624-Q1 can handle –10V at its inputs, which improves robustness in systems with moderate ground bouncing. The inputs are independent of supply voltage and can be connected to most controller outputs for maximum control flexibility. An independent enable signal allows the power stage to be controlled independently of main control logic. In the event of a system fault, the gate driver can quickly shut-off by pulling enable low. Many high-frequency switching power supplies exhibit noise at the gate of the power device, which can get injected into the output pin on the gate driver and can cause the driver to malfunction. The device's transient reverse current and reverse voltage capability allow it to tolerate noise on the gate of the power device or pulse-transformer and avoid driver malfunction.
The UCC27624-Q1 also features undervoltage lockout (UVLO) for improved system robustness. When there is not enough bias voltage to fully enhance the power device, the gate driver output is held low by the strong internal pull down MOSFET.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
UCC27624-Q1 | D (SOIC 8) | 4.90mm × 3.91mm |
UCC27624-Q1 | DGN (VSSOP 8) | 3.00mm × 3.00mm |
UCC27624-Q1 | DSD (WSON 8) | 3.00mm × 3.00mm |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | DGN DSD | D | ||
ENA | 1 | 1 | I | Enable input for Channel A. Biasing ENA, LOW will disable Channel A output regardless of the state of INA. Pulling ENA, HIGH enables the Channel A output. If ENA is left floating, Channel A is enabled by default due to an internal pullup resistor. It is recommended to connect this pin to VDD if unused. |
ENB | 8 | 8 | I | Enable input for Channel B. Biasing ENB, LOW disables Channel B output regardless of the state of INB. Pulling ENB, HIGH enables the Channel B output. If ENB is left floating, Channel B is enabled by default due to an internal pullup resistor. It is recommended to connect this pin to VDD if unused. |
GND | 3 | 3 | — | Ground: All signals are referenced to this pin. |
INA | 2 | 2 | I | Input to Channel A. INA is the non-inverting input of the UCC27624-Q1 device. OUTA is held LOW if INA is unbiased or floating by default due to an internal pulldown resistor. Connect this pin to GND if unused. |
INB | 4 | 4 | I | Input to Channel B. INB is the non-inverting input of the UCC27624-Q1 device. OUTB is held LOW if INB is unbiased or floating by default due to an internal pulldown resistor. Connect this pin to GND if unused. |
OUTA | 7 | 7 | O | Channel A Output |
OUTB | 5 | 5 | O | Channel B Output |
VDD | 6 | 6 | I | Bias supply input. Bypass this pin with two ceramic capacitors, generally ≥ 1 μF and 0.1 μF, which are referenced to GND pin of this device. |
Thermal Pad | — | — | Connect to GND through large copper plane. This pad is not a low-impedance path to GND. |