Table 4. UCC27712-Q1 Design Requirements

9.2.2.1 Selecting HI and LI Low Pass Filter Components (R_HI, R_LI, C_HI, C_LI)

It is recommended that users avoid shaping the input signals to the gate driver in an attempt to slow down (or delay) the signal at the driver output. However it is good practice to have a small RC filter added between PWM controller and input pin of UCC27712-Q1 to filter the high frequency noise, like R_HI/C_HI and R_LI/C_LI which is shown in Figure 44.

Such a filter should use a R_HI/R_LI in the range of 10 Ω to 100 Ω and a C_HI/C_LI between 10 pF and 220 pF. In the example, a R_HI/R_LI = 49.9 Ω and a C_HI/C_LI = 33 pF are selected.

9.2.2.2 Selecting Bootstrap Capacitor (C_BOOT)

The bootstrap capacitor should be sized to have more than enough energy to drive the gate of FET Q1 high, and maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with:

Equation 1.

This design example targets a boot capacitor ripple voltage of 0.5 V. Therefore, the absolute minimum C_BOOT requirement is:

Equation 2.

In practice, the value of C_BOOT needs to be greater than the calculated value. This allows for capacitance shift from DC bias and temperature, and also skipped cycles that occur during load transients. For this design example 2x 220-nF capacitors were chosen for the bootstrap capacitor.

Equation 3.

9.2.2.3 Selecting VDD Bypass/Holdup Capacitor (C_VDD) and R_bias

The VDD capacitor (C_VDD) should be chosen to be at least 10 times larger than C_BOOT so there is minimal voltage drop on the VDD capacitor when charging the boot capacitor .  For this design example a 4.7-µF capacitor was selected.

Equation 4.

A 10-Ω resistor R_BIAS in series with bias supply and VDD pin is recommended to make the VDD ramp up time larger than 20 µs to minimize LO and HO rising as shown in Figure 45

Figure 45. VDD/HB-HS Fast Ramp Up

9.2.2.4 Selecting Bootstrap Resistor (R_BOOT)

Resistor R_BOOT is selected to limit the current in D_BOOT and limit the ramp up slew rate of voltage of HB-HS to avoid the phenomenon shown in Figure 45.  It is recommended when using the UCC27712-Q1 that R_BOOT is between 2 Ω and 20 Ω.  For this design we selected an R_BOOT current limiting resistor of 2.2 Ω.  The bootstrap diode current (I_DBOOT(pk)) was limited to roughly 5.0 A.

Equation 5.

The power dissipation capability of the bootstrap resistor is important. The bootstrap resistor must be able to withstand the short period of high power dissipation during the initial charging sequence of the boot-strap capacitor. This energy is equivalent to 1/2 × CBOOT × V². This energy is dissipated during the charging time of the bootstrap capacitor (~3 × R_BOOT × C_BOOT). Special attention must be paid to use a bigger size R_BOOT when a bigger value of C_BOOT is chosen.

9.2.2.5 Selecting Gate Resistor R_ON/R_OFF

Resistor R_ON and R_OFF are sized to achieve the following:

• Limit ringing caused by parasitic inductances and capacitances.
• Limit ringing caused by high voltage/current switching dV/dt, dI/dt, and body diode reverse recovery.
• Fine-tune gate drive strength to optimize switching loss.
• Reduce electromagnetic interference (EMI).

As mentioned in Output Stage, the UCC27712-Q1 has a pull up structure with a P-channel MOSFET providing a peak source current of 1.8A.

For this example 3.3-Ω resistors for R_ON and 2.2-Ω resistors for R_OFF were selected to provide damping for ringing and ample gate drive current.

Equation 6.

Therefore the peak source current can be predicted with:

Equation 7.

Equation 8.

where

• R_ON: External turn-on resistance
• R_{GFET_Int}: Power transistor internal gate resistance, found in the power transistor datasheet.
• I_O+ = Peak source current. The maximum values between 1.8 A, the UCC27712-Q1 peak source current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 9.

Equation 10.

Therefore, the high-side and low side peak source current is 1.6 A. Similarly, the peak sink current can be calculated with:

Equation 11.

Equation 12.

where

• R_OFF: External turn-off resistance
• V_DGATE: The diode forward voltage drop which is in series with R_OFF. The diode in this example is an MBRM130L.
• I_O- = Peak sink current. The maximum values between 2.8 A, the UCC27712-Q1 peak sink current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 13.

Equation 14.

9.2.2.6 Selecting Bootstrap Diode

A fast recovery diode should be chosen to avoid charge being taken away from the bootstrap capacitor. Thus, a fast reverse recovery time t_RR, low forward voltage V_F and low junction capacitance is recommended.

Suggested parts include MURA160T3G and BYG20J.

9.2.2.7 Estimate the UCC27712-Q1 Power Losses (P_UCC27712-Q1)

The power losses of UCC27712-Q1 (P_UCC27712-Q1) are estimated by calculating losses from several components. The gate drive loss in the UCC27712-Q1 is typically dominated by gate drive losses associated with charging and discharging the power device gate charge. There are other losses to consider especially if operating at high switching frequencies outlined below.

To determine the UCC27712-Q1 operating with no driver load, refer to the Typical Characteristics Figure 26 for IDD and IHB to determine the operating current at the appropriate f_SW. The operating current power losses with no driver load are calculated in Equation 15:

Equation 15.

Static losses due to leakage current (I_BL) are calculated from the HB high-voltage node as shown in Equation 16:

Equation 16.

Equation 17 calculates dynamic losses during the operation of the level shifter at HO turn-off edge. Q_P, typically 0.6 nC, is the charge absorbed by the level shifter during operation at each edge. Please note that if high-voltage switching occurs during HO turn-on as well (as in the case of ZVS topologies), then the power loss due to this component must be effectively doubled.

Equation 17.

where

• V_HV: DC link high voltage input in V
• f_SW: Switching frequency of converter in Hz.

Dynamic losses incurred due to the gate charge while driving the FETs Q1 and Q2 are calculated Equation 18. Please note that this component typically dominates over the dynamic losses related to the internal VDD and VHB switching logic circuitry in UCC27712-Q1. The losses incurred driving the gate charge are not all dissipated in the gate driver device, this includes losses in the external gate resistance and internal power switch gate resistance.

Equation 18.

The UCC27712-Q1 gate driver loss on the output stage ,P_GDO, is part of P_QG1,QG2. If the external gate resistances are zero most of the P_QG1,QG2 will be dissipated in the UCC27712-Q1. If there are external gate resistances, the total loss will be distributed between the gate driver pull-up/down resistances and the external gate resistances.

The gate drive power dissipated within the UCC27712-Q1 driver can be determined by Equation 19:

Equation 19.

In this example the gate drive related losses are approximately 60mW as shown in Equation 20:

Equation 20.

For the conditions, VDD=12V, VHB = 400V, HO On-state Duty cycle D = 50%, Q_G = 68nC, f_SW = 100kHz, the total power loss in UCC27712-Q1 driver for a half bridge power supply topology can be estimated as follows:

Equation 21.

9.2.2.8 Estimating Junction Temperature

The junction temperature can be estimated with:

Equation 22.

where

• T_C is the UCC27712-Q1 case-top temperature measured with a thermocouple or some other instrument. and
• Ѱ_JT is the junction-to-top characterization parameter from the Thermal Information table. Importantly.

Using the junction-to-top characterization parameter (Ѱ_JT) instead of the junction-to-case thermal resistance (R_θJC) can greatly improve the accuracy of estimating the junction temperature. The majority of the power dissipation of most devices is released into the PCB through the package leads, whereas only a small percentage of the total dissipation is released through the top of the case (where thermocouple measurements are usually taken). R_θJC can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or a heatsink is applied to the device package. In other cases R_θJC will inaccurately estimate the true junction temperature of the device. Ѱ_JT is experimentally derived by assuming the amount of thermal energy dissipated through the top of the device will be similar in both the testing environment and the application environment. As long as the recommended layout guidelines are observed, junction temperature can be estimated accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package Thermal Metrics application report.

Additional Considerations: In the application example schematic there are 10-kΩ resistors across the gate and source terminals of FET Q1 and Q2.  These resistors are placed across these nodes to ensure FETs Q1 and Q2 are not turned on if the UCC27712-Q1 is not in place or properly soldered to the circuit board or if UCC27712-Q1 is in an unbiased state.

9.2.2.9 Operation With IGBT's

The UCC27712-Q1 is well suited for driving IGBT's in various applications including motor drive and inverters. The design procedure is as the previous MOSFET example but the VDD voltage is typically 15-V to drive IGBT devices. Use the power transistor parameters and application specifications to determine the detail design and component values. See Figure 46 below for a typical IGBT application.

Figure 46. Typical IGBT Application Schematic

Refer to Figure 47 below for the UCC27712-Q1 driving 40-A, 650-V IGBT's in a high voltage sync buck configuration. The input voltage is 400 V, output 100 V with a 150-W output load. Channel 1 is the inductor current, Channel 2 is high-side IGBT VGE, Channel 3 is low-side IGBT VGE, and Channel 4 is the switch node or HS voltage.

Figure 47. IGBT Sync-Buck Operating at 400 V and 150 W