SLUSCW3 August   2017 UCC27712-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dynamic Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Under Voltage Lockout
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Level Shift
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 8.3.7 Parasitic Diode Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Minimum Input Pulse Operation
      2. 8.4.2 Output Interlock and Dead Time
      3. 8.4.3 Operation Under 100% Duty Cycle Condition
      4. 8.4.4 Operation Under Negative HS Voltage Condition
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 9.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 9.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 9.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 9.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 9.2.2.6 Selecting Bootstrap Diode
        7. 9.2.2.7 Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1)
        8. 9.2.2.8 Estimating Junction Temperature
        9. 9.2.2.9 Operation With IGBT's
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise noted), currents are positive into and negative out of the specified terminal.(1)
PARAMETER MIN MAX UNIT
Input voltage HI, LI (2) –5 22 V
VDD supply voltage –0.3 22
HB –0.3 700
HB–HS –0.3 22
Output voltage HO DC HS–0.3 HB+0.3 V
Transient, less than 100 ns(3) HS–2 HB+0.3
LO DC –0.3 VDD+0.3 V
Transient, less than 100 ns(3) –2 VDD+0.3
Output current HO, LO IOUT_PULSED (100 ns) 2.8/–1.8 A
IOUT_DC 0.15
dVHS/dt Allowable offset supply voltage transient –50 50 V/ns
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum voltage on the input pins is not restricted by the voltage on the VDD pin
Values are verified by characterization on bench.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±1500 V
Charged-device model (CDM), per AEC Q100-011 ±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Recommended Operating Conditions

All voltages are with respect to COM, over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage IGBT applications 10 20 V
MOSFET applications 10 17
HB–HS Driver bootstrap voltage IGBT applications 10 20
MOSFET applications 10 17
HS Source terminal voltage(1) –11 600
HI, LI Input voltage with respect to COM –4 20
TA Ambient temperature –40 125 °C
Logic operational for HS of –11 V to +600 V at HB–HS = 15 V

Thermal Information

THERMAL METRIC(1) UCC27712-Q1 UNIT
(SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 108.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.5 °C/W
RθJB Junction-to-board thermal resistance 57.9 °C/W
ψJT Junction-to-top characterization parameter 15.3 °C/W
ψJB Junction-to-board characterization parameter 57.2 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY BLOCK
VVDD ON Turn-on threshold voltage of VDD 8.0 8.9 9.8 V
VVDD OFF Turn-off threshold voltage of VDD 7.5 8.4 9.3
VVDD HYS Hysteresis of VDD 0.5
VVHB ON Turn-on threshold voltage of VHB–VHS 7.2 8.2 9.2
VVHB OFF Turn-off threshold voltage of VHB–VHS 6.4 7.3 8.3
VVHB HYS Hysteresis of VHB–VHS 0.5 0.9
IQ Total quiescent supply current HI = LI = 0 V or 5 V, DC on/off state 180 255 420 µA
IQVDD Quiescent VDD-COM supply current HI = LI = 0 V or 5 V, DC on/off state 190 320
IQBS Quiescent HB-HS supply current HI = 0 V or 5 V, HO in DC on/off state 65 100
IBL Bootstrap supply leakage current HB = HS = 600 V 20
IOP Dynamic operating current HI = LI = 0 V or 5 V, f = 100 kHz, duty = 50%, CL= 1 nF 3800(1) 4500
INPUT BLOCK
VINH Input Pin (HI, LI) high threshold 1.6 2.0 2.4 V
VINL Input Pin (HI, LI) low threshold 0.8 1.2 1.5
VINHYS Input Pin (HI, LI) threshold hysteresis 0.8
IINL HI, LI input low bias current HI, LI = 0 V –5 0 5 µA
IINH HI, LI input high bias current HI, LI = 5 V 1.7 70
OUTPUT BLOCK
VDD-VLOH LO output high voltage LI = 5 V, ILO = –20 mA 60 136 mV
VHB-VHOH HO output high voltage HI = 5 V, IHO = –20 mA 60 136
VLOL LO output low voltage LI = 0 V, ILO = 20 mA 30 80
VHOL HO output low voltage HI = 0 V, IHO = 20 mA 30 80
RLOL, RHOL LO, HO output pull-down resistance ILO = IHO = 20 mA 1.5 4 Ω
RLOH, RHOH LO, HO output pull-up resistance ILO = IHO = –20 mA 3.0 6.8
IGPK-(1) HO, LO output low short circuit pulsed current HI = LI = 0 V, HO = LO = 15 V, PW < 10 µs 2.8 A
IGPK+(1) HO, LO output high short circuit pulsed current HI = LI = 5 V, HO = LO = 0 V, PW < 10 µs –1.8
Ensured by design, not tested in production

Dynamic Electrical Characteristics

At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DYNAMIC CHARACTERISTICS
tPDLH Turn-on propagation delay (without deadtime) LI to LO, HI to HO, HS = COM = 0 V 100 160 ns
tPDHL Turn-off propagation delay LI to LO, HI to HO, HS = COM = 0 V 100 160
tPDRM Low-to-high delay matching 5 30
tPDFM High-to-low delay matching 12 30
tRISE Turn-on rise time 10% to 90%, HO/LO with 1000-pF load 16 50
tFALL Turn-off fall time 10% to 90%, HO/LO with 1000-pF load 10 30
tON Minimum HI/LI ON pulse that changes output state 0-V to 5-V input signal on HI and LI pins 25 45
tOFF Minimum HI/LI OFF pulse that changes output state 5-V to 0-V input signal on HI and LI pins 35 45
DT Deadtime Internal deadtime for Interlock 100 150 200
UCC27712-Q1 typtest_slusce9.gif Figure 1. Typical Test Timing Diagram

Typical Characteristics

UCC27712-Q1 D001_slusce9.gif
Figure 2. Low-Side, Turn-On Propagation Delay vs Temperature
UCC27712-Q1 D003_slusce9.gif
Figure 4. High-Side, Turn-On Propagation Delay vs Temperature
UCC27712-Q1 D005_slusce9.gif
Figure 6. Turn-On Delay Matching vs Temperature
UCC27712-Q1 d007new_slusce9.gif
Figure 8. High-Side Propagation Delay vs HS
UCC27712-Q1 D009_slusce9.gif
Figure 10. LO Fall Time with 1000-pF Load vs Temperature
UCC27712-Q1 D0011_slusce9.gif
Figure 12. HO Fall Time with 1000-pF Load vs Temperature
UCC27712-Q1 D0013_slusce9.gif
Figure 14. VHB-VHS UVLO Thresholds vs Temperature
UCC27712-Q1 D0015_slusce9.gif
Figure 16. HI/LI Pin High Threshold vs Temperature
UCC27712-Q1 D0017_slusce9.gif
Figure 18. HI/LI Pin Hysteresis vs Temperature
UCC27712-Q1 D0019_slusce9.gif
Figure 20. HO Output Pull-Down Resistance vs Temperature
UCC27712-Q1 D0021_slusce9.gif
Figure 22. HO Output Pull-Up Resistance vs Temperature
UCC27712-Q1 D0023_slusce9.gif
Figure 24. Quiescent HB to HS Supply Current vs Temperature
UCC27712-Q1 D0025_slusce9.gif
Figure 26. VDD and HB Operating Current with No Load vs Switching Frequency
UCC27712-Q1 D0027_slusce9.gif
Figure 28. VDD and HB Operating Current with 4700-pF Load vs Switching Frequency
UCC27712-Q1 D002_slusce9.gif
Figure 3. Low-Side, Turn-Off Propagation Delay vs Temperature
UCC27712-Q1 D004_slusce9.gif
Figure 5. High-Side, Turn-Off Propagation Delay vs Temperature
UCC27712-Q1 D006_slusce9.gif
Figure 7. Turn-Off Delay Matching vs Temperature
UCC27712-Q1 D008_slusce9.gif
Figure 9. LO Rise Time with 1000-pF Load vs Temperature
UCC27712-Q1 D0010_slusce9.gif
Figure 11. HO Rise Time with 1000-pF Load vs Temperature
UCC27712-Q1 D0012_slusce9.gif
Figure 13. VDD UVLO Thresholds vs Temperature
UCC27712-Q1 D0014_slusce9.gif
Figure 15. VDD and VHB-VHS UVLO Hysteresis vs Temperature
UCC27712-Q1 D0016_slusce9.gif
Figure 17. HI/LI Pin Low Threshold vs Temperature
UCC27712-Q1 D0018_slusce9.gif
Figure 19. LO Output Pull-Down Resistance vs Temperature
UCC27712-Q1 D0020_slusce9.gif
Figure 21. LO Output Pull-Up Resistance vs Temperature
UCC27712-Q1 D0022_slusce9.gif
Figure 23. Total Quiescent VDD plus HB Supply Current vs Temperature
UCC27712-Q1 D0024_slusce9.gif
Figure 25. HB to COM Bootstrap Supply Leakage Current vs Temperature
UCC27712-Q1 D0026_slusce9.gif
Figure 27. VDD and HB Operating Current with 1000-pF Load vs Switching Frequency