SGLS121D December 2002 – June 2020 UCC2800-Q1 , UCC2801-Q1 , UCC2802-Q1 , UCC2803-Q1 , UCC2804-Q1 , UCC2805-Q1
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Detailed Pin Description
- 9.3.2 Undervoltage Lockout (UVLO)
- 9.3.3 Self-Biasing, Active Low Output
- 9.3.4 Reference Voltage
- 9.3.5 Oscillator
- 9.3.6 Synchronization
- 9.3.7 PWM Generator
- 9.3.8 Minimum Off-Time Setting (Dead-Time Control)
- 9.3.9 Leading Edge Blanking
- 9.3.10 Minimum Pulse Width
- 9.3.11 Current Limiting
- 9.3.12 Overcurrent Protection and Full Cycle Restart
- 9.3.13 Soft Start
- 9.3.14 Slope Compensation
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.2.2.6.2 Compensation Loop
For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth of a CCM flyback, fBW, is limited to ¼ of the RHP zero frequency, or approximately 1.9 kHz using Equation 36.
The gain of the open-loop power stage at fBW is equal to –22.4 dB and the phase at fBW is equal to –87°. First step is to choose the output voltage sensing resistor values. The output sensing resistors are selected based on the allowed power consumption and in this case, 1 mA of sensing current is assumed.
The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage sensing dividers RFBU and RFBB can be selected with Equation 37 and Equation 38.
Next step is to put the compensator zero fCZ at 190 Hz, which is 1/10 of the crossover frequency. Choose CZ as a fixed value of 10 nF and choose the zero resistor value according to Equation 39.
Then put a pole at the lower frequency of right half plane zero or the ESR zero. Based previous analysis, the right half plane zero is at 7.65 kHz and the ESR zero is at 6 kHz, the pole of the compensation loop must be put at 6 kHz. This pole can be added through the primary side error amplifier. RFB and CFB provide the necessary pole. Choosing RFB as 10 kΩ and the CFB is selected with Equation 40.
Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 41.
In this equation, the CTR is the current transfer ratio of the opto-coupler. Choose 1 as the nominal value for CTR. REG is the opto-pulldown resistor and 1 kΩ is chosen as a default value. The only value required in this equation is RLED. The entire loop gain must be equal to 1 at the crossover frequency. RLED is calculated accordingly as 1.62 kΩ.
The final close loop bode plots are show in Figure 36 and Figure 37. The converter achieves approximately 2-kHz crossover frequency and approximately 70o of phase margin.
TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability.
Figure 36. Converter Close Loop Bode Plot – Gain 
Figure 37. Converter Close Loop Bode Plot – Phase