UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller

7.3.2.1 VCC Undervoltage Lockout (UVLO)

During startup, Under-Voltage Lockout (UVLO) keeps the device in the off state until VCC rises above the 10.5-V enable threshold, VCC_ON. With a typical 1 V of hysteresis on UVLO to increase noise immunity, the device turns off when VCC drops to the 9.5-V disable threshold, VCC_OFF.

Figure 19. UVLO

If, during a brief ac-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current surge should the ac-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically, these capacitors can be discharged to less than 1.2 V within 150 ms of loss of VCC.

7.3.2.2 Input Brown-Out Protection (IBOP)

The sensed line-voltage input, VINS, provides a means for the designer to set the desired mains RMS voltage level at which the PFC pre-regulator should start-up, V_ACturnon, as well as the desired mains RMS level at which it should shut down, V_ACturnoff. This prevents unwanted sustained system operation at or below a brown-out voltage, where excessive line current could overheat components. In addition, because VCC bias is not derived directly from the line voltage, IBOP protects the circuit from low line conditions that may not trigger the VCC UVLO turn-off.

Figure 20. Input Brown-Out Protection

Input line voltage is sensed directly from the rectified ac mains voltage through a resistor-divider filter network providing a scaled and filtered value at the VINS input. IBOP will put the device into standby mode when VINS falls (high to low) below 0.8 V, VINS_{BROWNOUT_th}. The device comes out of standby when VINS rises (low to high) above 1.5 V, VINS_{ENABLE_th}. Bias current sourced from VINS, I_{VINS_0V}, is less than 0.1 μA. With a bias current this low, there is little concern for any set-point error caused by this current flowing through the sensing network. The highest praticable value resistance for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. Be aware that higher resistance values are more susceptible to noise pickup, but low-noise PCB layout techniques can help mitigate this. Also, depending on the resistor type used and its voltage rating, R_VINS1 should be implemented with multiple resistors in series to reduce voltage stresses.

First, select R_VINS1 based on choosing the highest reasonable resistance value available for typical applications.

Then select R_VINS2 based on this value:

Equation 1.

Power dissipated in the resistor network is:

Equation 2.

The filter capacitor, C_VINS, has two functions. First, to attenuate the voltage ripple to levels between the enable and brown-out threshold to prevent ripple on VINS from falsely triggering IBOP when the converter is operating at low line. Second, C_VINS delays the brown-out protection operation for a desired number of line-half-cycle periods while still having a good response to an actual brown-out event.

The capacitor is chosen so that it will discharge to the VINS_{BROWNOUT_th} level after a delay of N number of line ½-cycles to accommodate ac-line dropout ride-through requirements.

Equation 3.

Where,

Equation 4.

and V_ACmin is the lowest normal operating rms input voltage.

7.3.2.3 Output Overvoltage Protection (OVP)

V_OUT(OVP) is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold (5-V reference voltage + 5%), V_OVP. The normal control loop is bypassed and the GATE output is disabled until VSENSE falls below 5.25 V. V_OUT(OVP) is 420 V in a system with a 400-V rated output, for example.

7.3.2.4 Open Loop Protection/Standby (OLP/Standby)

If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage, causing VSENSE to fall below 0.8 V, the device is put in standby, a state where the PWM switching is halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature also gives the designer the option of pulling VSENSE low with an external switch.

7.3.2.5 ISENSE Open-Pin Protection (ISOP)

If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-up source drives ISENSE above 0.1 V so that a detector forces a state where the PWM switching is halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature avoids continual operation in OVP and severely distorted input current.

7.3.2.6 Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)

During normal operation, small perturbations on the PFC output voltage rarely exceed 5% deviation and the normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the output voltage drop exceeds -5%, an output under-voltage is detected (UVD) and Enhanced Dynamic Response (EDR) acts to speed up the slow response of the low-bandwidth voltage loop. During EDR, the transconductance of the voltage error amplifier is increased approximately 16 times to speed charging of the voltage-loop compensation capacitors to the level required for regulation. EDR is removed when VSENSE > 4.75 V. The EDR feature is not activated until soft start is completed.

Figure 21. OVP, UVD, OLP/ Standby, Soft Start Complete

Figure 22. Soft Start and Protection States

7.3.2.7 Over-Current Protection

Inductor current is sensed by R_ISENSE, a low value resistor in the return path of input rectifier. The other side of the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is always negative. The voltage at ISENSE is buffered by a fixed gain of -1.0 to provide a positive internal signal to the current functions. There are two over-current protection features; Soft Over-Current (SOC) protects against an overload on the output and Peak Current Limit (PCL) protects against inductor saturation.

Figure 23. Soft Over Current/ Peak Current Limit

7.3.2.8 Soft Over Current (SOC)

Soft Over-Current (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE reaches -0.73 V, affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty cycle.

7.3.2.9 Peak Current Limit (PCL)

Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE reaches -1.08 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked to improve noise immunity against false triggering.

7.3.2.10 Current Sense Resistor, R_ISENSE

The current sense resistor, R_ISENSE, is sized using the minimum threshold value of Soft Over Current (SOC), V_SOC(min) = 0.66 V. To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle, the resistor is sized for an overload current of 10% more than the peak inductor current,

Equation 5.

Since R_ISENSE sees the average input current, worst-case power dissipation occurs at input low-line when input current is at its maximum. Power dissipated by the sense resistor is given by:

Equation 6.

Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor reaches the PCL threshold, V_PCL. The absolute maximum peak current, I_PCL, is given by:

Equation 7.