SGLS121D December   2002  – June 2020 UCC2800-Q1 , UCC2801-Q1 , UCC2802-Q1 , UCC2803-Q1 , UCC2804-Q1 , UCC2805-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Detailed Pin Description
        1. 9.3.1.1 COMP
        2. 9.3.1.2 FB
        3. 9.3.1.3 CS
        4. 9.3.1.4 RC
        5. 9.3.1.5 GND
        6. 9.3.1.6 OUT
        7. 9.3.1.7 VCC
        8. 9.3.1.8 Pin 8 (REF)
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Self-Biasing, Active Low Output
      4. 9.3.4  Reference Voltage
      5. 9.3.5  Oscillator
      6. 9.3.6  Synchronization
      7. 9.3.7  PWM Generator
      8. 9.3.8  Minimum Off-Time Setting (Dead-Time Control)
      9. 9.3.9  Leading Edge Blanking
      10. 9.3.10 Minimum Pulse Width
      11. 9.3.11 Current Limiting
      12. 9.3.12 Overcurrent Protection and Full Cycle Restart
      13. 9.3.13 Soft Start
      14. 9.3.14 Slope Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation
      2. 9.4.2 UVLO Mode
      3. 9.4.3 Soft Start Mode
      4. 9.4.4 Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Current Sensing Network
        2. 10.2.2.2 Gate Drive Resistor
        3. 10.2.2.3 Vref Capacitor
        4. 10.2.2.4 RTCT
        5. 10.2.2.5 Start-Up Circuit
        6. 10.2.2.6 Voltage Feedback Compensation
          1. 10.2.2.6.1 Power Stage Gain, Zeroes, and Poles
          2. 10.2.2.6.2 Compensation Loop
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Related Links
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

–40°C ≤ TA ≤ 125°C for UCC280x-Q1. VCC = 10 V(1), RT = 100 k from REF to RC, CT = 330 pF from RC to GND, 0.1-uF capacitor from VCC to GND, 0.1-uF capacitor from VREF to GND, and TA= TJ (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
Output voltage TJ= 25°C, I = 0.2 mA, UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and UCC2804-Q1 4.925 5 5.075 V
TJ= 25°C, I = 0.2 mA, UCC2803-Q1 and UCC2805-Q1 3.94 4 4.06
Load regulation 0.2 mA < I < 5 mA UCC280x-Q1 10 30 mV
Line regulation TJ = 25°C, VCC = 10 V to clamp (IVCC = 25 mA) 1.9 mV/V
TJ = –40°C to 125°C, VCC = 10 V to clamp (IVCC = 25 mA) UCC280x-Q1 2.5
Total variation UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and UCC2804-Q1(5) 4.88 5 5.1 V
UCC2803-Q1 and UCC2805-Q1(5) 3.9 4 4.08
Output noise voltage 10 Hz ≤ f ≤ 10 kHz, TJ= 25°C(7) 130 µV
Long term stability TA = 125°C, 1000 hours(7) 5 mV
Output short circuit –5 –35 mA
OSCILLATOR
Oscillator frequency UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, UCC2804-Q1(2) 40 46 52 kHz
UCC2803-Q1 and UCC2805-Q1(2) 26 31 36
Temperature stability(7) 2.5 %
Amplitude peak-to-peak 2.25 2.4 2.55 V
Oscillator peak voltage 2.45 V
ERROR AMPLIFIER
Input voltage COMP = 2.5 V, UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, and UCC2804-Q1 2.44 2.5 2.56 V
COMP = 2 V, UCC2803-Q1 and UCC2805-Q1 1.95 2 2.05
Input bias current –1 1 µA
Open loop voltage gain 60 80 dB
COMP sink current FB = 2.7 V, COMP = 1.1 V UCC280x-Q1 0.3 3.5 mA
COMP source current FB = 1.8 V, COMP = REF – 1.2 V –0.2 –0.5 –0.8 mA
Gain bandwidth product(7) 2 MHz
PWM
Maximum duty cycle UCC2800-Q1, UCC2802-Q1, and UCC2803-Q1 97 99 100 %
UCC2801-Q1, UCC2804-Q1, and UCC2805-Q1 48 49 50
CURRENT SENSE
Gain(3) 1.1 1.65 1.8 V/V
Maximum input signal COMP = 5 V(4) 0.9 1 1.1 V
Input bias current –200 200 nA
CS blank time 50 100 150 ns
Overcurrent threshold 1.42 1.55 1.68 V
COMP to CS offset CS = 0 V 0.45 0.9 1.35 V
OUTPUT
OUT low level I = 20 mA, all parts 0.1 0.4 V
I = 200 mA, all parts 0.35 0.9
I = 50 mA, VCC = 5 V, UCC2803-Q1 and UCC2805-Q1 0.15 0.4
I = 20 mA, VCC = 0 V, all parts 0.7 1.2
OUT high VSAT (VCC-OUT) I = 20 mA, all parts 0.15 0.4 V
I = 200 mA, all parts 1 1.9
I = 50 mA, VCC = 5 V, UCC2803-Q1 and UCC2805-Q1 0.4 0.9
Rise time CL = 1 nF 41 70 ns
Fall time CL = 1 nF 44 75 ns
UNDERVOLTAGE LOCKOUT
Start threshold(6) UCC2800-Q1 6.6 7.2 7.8 V
UCC2801-Q1 8.6 9.4 10.2
UCC2802-Q1 and UCC2804-Q1 11.5 12.5 13.5
UCC2803-Q1 and UCC2805-Q1 3.7 4.1 4.5
Stop threshold(6) UCC2800-Q1 6.3 6.9 7.5 V
UCC2801-Q1 6.8 7.4 8
UCC2802-Q1 and UCC2804-Q1 7.6 8.3 9
UCC2803-Q1 and UCC2805-Q1 3.2 3.6 4
Start to stop hysteresis UCC2800-Q1 0.12 0.3 0.48 V
UCC2801-Q1 1.6 2 2.4
UCC2802-Q1 and UCC2804-Q1 3.5 4.2 5.1
UCC2803-Q1 and UCC2805-Q1 0.2 0.5 0.8
SOFT START
COMP rise time FB = 1.8 V, rise from 0.5 V to REF – 1 V 4 10 ms
OVERALL
Start-up current VCC < start threshold 0.1 0.2 mA
Operating supply current FB = 0 V, CS = 0 V 0.5 1 mA
VCC internal Zener voltage ICC = 10 mA(6)(8) 12 13.5 15 V
VCC internal Zener voltage minus start threshold voltage UCC2802-Q1 and UCC2804-Q1(6) 0.5 1 V
(1) Adjust VCC above the start threshold before setting at 10 V.
(2) Oscillator frequency for the UCCx800, UCC2802, and UCC2803 is the output frequency. Oscillator frequency for the UCC2801, UCC2804, and UCC2805 is twice the output frequency.
(3) Gain is defined by: A = ΔVCOMP / Δ VCS. 0 ≤ VCS ≤ 0.8 V
(4) Parameter measured at trip point of latch with Pin 2 at 0 V.
(5) Total variation includes temperature stability and load regulation.
(6) Start threshold, stop threshold, and Zener shunt thresholds track one another.
(7) Ensured by design. Not 100% tested in production.
(8) The device is fully operating in clamp mode, as the forcing current is higher than the normal operating supply current.