SLUS270G March   1999  – May 2020 UCC2800 , UCC2801 , UCC2802 , UCC2803 , UCC2804 , UCC2805

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Detailed Pin Description
        1. 9.3.1.1 COMP
        2. 9.3.1.2 FB
        3. 9.3.1.3 CS
        4. 9.3.1.4 RC
        5. 9.3.1.5 GND
        6. 9.3.1.6 OUT
        7. 9.3.1.7 VCC
        8. 9.3.1.8 Pin 8 (REF)
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Self-Biasing, Active Low Output
      4. 9.3.4  Reference Voltage
      5. 9.3.5  Oscillator
      6. 9.3.6  Synchronization
      7. 9.3.7  PWM Generator
      8. 9.3.8  Minimum Off-Time Setting (Dead-Time Control)
      9. 9.3.9  Leading Edge Blanking
      10. 9.3.10 Minimum Pulse Width
      11. 9.3.11 Current Limiting
      12. 9.3.12 Overcurrent Protection and Full Cycle Restart
      13. 9.3.13 Soft Start
      14. 9.3.14 Slope Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation
      2. 9.4.2 UVLO Mode
      3. 9.4.3 Soft Start Mode
      4. 9.4.4 Fault Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Current Sensing Network
        2. 10.2.2.2 Gate Drive Resistor
        3. 10.2.2.3 Vref Capacitor
        4. 10.2.2.4 RTCT
        5. 10.2.2.5 Start-Up Circuit
        6. 10.2.2.6 Voltage Feedback Compensation
          1. 10.2.2.6.1 Power Stage Gain, Zeroes, and Poles
          2. 10.2.2.6.2 Compensation Loop
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Support Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
    5. 13.5 Related Links
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.2.2.6.2 Compensation Loop

For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth of a CCM flyback, fBW, is limited to ¼ of the RHP zero frequency, or approximately 1.9 kHz using Equation 36.

Equation 36. GUID-C1FEA277-562F-4D28-A2F6-491CEACE4196-low.gif

The gain of the open-loop power stage at fBW is equal to –22.4 dB and the phase at fBW is equal to –87°. First step is to choose the output voltage sensing resistor values. The output sensing resistors are selected based on the allowed power consumption and in this case, 1 mA of sensing current is assumed.

The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage sensing dividers RFBU and RFBB can be selected with Equation 37 and Equation 38.

Equation 37. GUID-720E757A-31C6-4EF8-B4F7-5AC84E117353-low.gif
Equation 38. GUID-4AA50C5D-F125-4B4C-BB20-B8B7FD789E04-low.gif

Next step is to put the compensator zero fCZ at 190 Hz, which is 1/10 of the crossover frequency. Choose CZ as a fixed value of 10 nF and choose the zero resistor value according to Equation 39.

Equation 39. GUID-6CE8978B-AE39-4D6A-8B0A-5364F4BFC6BC-low.gif

Then put a pole at the lower frequency of right half plane zero or the ESR zero. Based previous analysis, the right half plane zero is at 7.65 kHz and the ESR zero is at 6 kHz, the pole of the compensation loop must be put at 6 kHz. This pole can be added through the primary side error amplifier. RFB and CFB provide the necessary pole. Choosing RFB as 10 kΩ and the CFB is selected with Equation 40.

Equation 40. GUID-C70AD850-70FD-427B-B3FE-DD54DC784201-low.gif

Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 41.

Equation 41. GUID-63046EB9-88AC-475D-897E-D4901C90C80C-low.gif

In this equation, the CTR is the current transfer ratio of the opto-coupler. Choose 1 as the nominal value for CTR. REG is the opto-pulldown resistor and 1 kΩ is chosen as a default value. The only value required in this equation is RLED. The entire loop gain must be equal to 1 at the crossover frequency. RLED is calculated accordingly as 1.62 kΩ.

The final close loop bode plots are show in Figure 10-4 and Figure 10-5. The converter achieves approximately 2-kHz crossover frequency and approximately 70o of phase margin.

TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability.

GUID-4B48C0B1-29D9-4B91-8C6D-C0EC01AAF6EA-low.gifFigure 10-4 Converter Close Loop Bode Plot – Gain
GUID-BCF6FA67-E2FE-4F30-9894-007F2247F654-low.gifFigure 10-5 Converter Close Loop Bode Plot – Phase