CS is the input to the current sense comparators. The UCC280x family has two different current sense comparators: the PWM comparator and an overcurrent comparator.

The UCC280x family contains digital current sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking, means that in most applications, no analog filtering (RC filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS to OUT propagation delay. Note, however, that the minimum non-zero On-time of the OUT signal is directly affected by the leading-edge-blanking and the CS to OUT propagation delay.

The overcurrent comparator is only intended for fault sensing, and exceeding the overcurrent threshold causes a soft-start cycle.

OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±750 mA. OUT is actively held low when VCC is below the UVLO threshold.

The high-current power driver consists of FET output devices, which can switch all of the way to GND and all of the way to V_CC. The output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external schottky clamp diodes are not required.

RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.

The frequency of oscillation can be estimated with the following equations:

Equation 1.

Equation 2.

where

• frequency is in Hz
• resistance is in Ω
• capacitance is in farads

The recommended range of timing resistors is between 10 k and 200 k, and timing capacitor is 100 pF to 1000 pF. Never use a timing resistor less than 10 k.

REF is the voltage reference for the error amplifier, and also for many other functions on the IC. REF is also used as the logic power supply for high-speed switching logic on the IC.

When VCC is greater than 1 V and less than the UVLO threshold, REF is pulled to ground through a 5-kΩ resistor. This means that REF can be used as a logic output indicating power system status. It is important for reference stability that REF is bypassed to GND with a ceramic capacitor as close to the pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. A minimum of 0.1-μF ceramic is required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference.

To prevent noise problems with high speed switching transients, bypass REF to ground with a ceramic capacitor very close to the IC package.

VCC is the power input connection for this device. In normal operation, VCC is powered through a current limiting resistor. Although quiescent VCC current is very low, total supply current is higher depending on OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Q_g), average OUT current can be calculated from:

Equation 3.

To prevent noise problems, bypass VCC to GND with a ceramic capacitor as close to the VCC pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. There must be a minimum of 1 µF in parallel with a 0.1-µF ceramic capacitor from VCC to ground placed close to the device.