SLUSAO7C September   2011  – July 2024 UCC28063

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Principles of Operation
      2. 7.3.2  Natural Interleaving
      3. 7.3.3  On-Time Control, Maximum Frequency Limiting, and Restart Timer
      4. 7.3.4  Distortion Reduction
      5. 7.3.5  Zero-Current Detection and Valley Switching
      6. 7.3.6  Phase Management and Light-Load Operation
      7. 7.3.7  External Disable
      8. 7.3.8  Improved Error Amplifier
      9. 7.3.9  Soft Start
      10. 7.3.10 Brownout Protection
      11. 7.3.11 Dropout Detection
      12. 7.3.12 VREF
      13. 7.3.13 VCC
      14. 7.3.14 Control of Downstream Converter
      15. 7.3.15 System Level Protections
        1. 7.3.15.1 Failsafe OVP - Output Overvoltage Protection
        2. 7.3.15.2 Overcurrent Protection
        3. 7.3.15.3 Open-Loop Protection
        4. 7.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 7.3.15.5 Phase-Fail Protection
        6. 7.3.15.6 CS-Open, TSET-Open and -Short Protection
        7. 7.3.15.7 Thermal Shutdown Protection
        8. 7.3.15.8 AC-Line Brownout and Dropout Protections
        9. 7.3.15.9 Fault Logic Diagram
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Inductor Selection
        2. 8.2.2.2  ZCD Resistor Selection (RZA, RZB)
        3. 8.2.2.3  HVSEN
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Selecting (RS) For Peak Current Limiting
        6. 8.2.2.6  Power Semiconductor Selection (Q1, Q2, D1, D2)
        7. 8.2.2.7  Brownout Protection
        8. 8.2.2.8  Converter Timing
        9. 8.2.2.9  Programming VOUT
        10. 8.2.2.10 Voltage Loop Compensation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 8.2.3.2 Brownout Protection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Related Parts
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Detailed Pin Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.14 Control of Downstream Converter

In the UCC28063, the PWMCNTL pin can be used to coordinate the PFC stage with a downstream converter. Through the HVSEN pin, the PFC output voltage is monitored. A 12-μA current source (IHV_HYS) is enabled as long as the output voltage remains below a programmed threshold. When the output voltage exceeds that threshold, PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. At the same time the current source is disabled, providing hysteresis for a lower threshold at which the downstream converter should be turned off. The enable/disable hysteresis is adjusted through the HVSEN voltage-divider ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection (OVP). When designing the voltage divider, make sure this FailSafe OVP level is set above normal VSENSE OVP levels.

Because there are two thresholds associated with the HVSEN input detected through a single resistor divider, the PWMCNTL turn-off voltage, VPWM-OFF, is linked to the FailSafe OVP voltage, VFLSF_OV, as shown by Equation 14:

Equation 14. UCC28063

Choosing either one first arbitrarily determines the other, so a trade-off may be necessary. The PWMCNTL turn-on voltage, VPWM-ON, is programmed by choosing the upper divider resistor value in consideration with the HVSEN hysteresis current, as shown in Equation 15 and Equation 16. The lower divider resistor is then calculated as shown in Equation 17.

Equation 15. UCC28063
Equation 16. UCC28063
Equation 17. UCC28063