SLUSAO7C September   2011  – July 2024 UCC28063

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Principles of Operation
      2. 7.3.2  Natural Interleaving
      3. 7.3.3  On-Time Control, Maximum Frequency Limiting, and Restart Timer
      4. 7.3.4  Distortion Reduction
      5. 7.3.5  Zero-Current Detection and Valley Switching
      6. 7.3.6  Phase Management and Light-Load Operation
      7. 7.3.7  External Disable
      8. 7.3.8  Improved Error Amplifier
      9. 7.3.9  Soft Start
      10. 7.3.10 Brownout Protection
      11. 7.3.11 Dropout Detection
      12. 7.3.12 VREF
      13. 7.3.13 VCC
      14. 7.3.14 Control of Downstream Converter
      15. 7.3.15 System Level Protections
        1. 7.3.15.1 Failsafe OVP - Output Overvoltage Protection
        2. 7.3.15.2 Overcurrent Protection
        3. 7.3.15.3 Open-Loop Protection
        4. 7.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 7.3.15.5 Phase-Fail Protection
        6. 7.3.15.6 CS-Open, TSET-Open and -Short Protection
        7. 7.3.15.7 Thermal Shutdown Protection
        8. 7.3.15.8 AC-Line Brownout and Dropout Protections
        9. 7.3.15.9 Fault Logic Diagram
    4. 7.4 Device Functional Modes
  9. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Inductor Selection
        2. 8.2.2.2  ZCD Resistor Selection (RZA, RZB)
        3. 8.2.2.3  HVSEN
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Selecting (RS) For Peak Current Limiting
        6. 8.2.2.6  Power Semiconductor Selection (Q1, Q2, D1, D2)
        7. 8.2.2.7  Brownout Protection
        8. 8.2.2.8  Converter Timing
        9. 8.2.2.9  Programming VOUT
        10. 8.2.2.10 Voltage Loop Compensation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 8.2.3.2 Brownout Protection
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Related Parts
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Detailed Pin Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40 °C < TJ = TA < 125 °C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VCC BIAS SUPPLY
VCCSHUNTVCC shunt voltage(1)IVCC = 10 mA222426V
IVCC(ULVO)VCC current, UVLOVCC = 11.4 V prior to turn-on95200µA
IVCC(stby)VCC current, disabledVSENSE = 0 V100200
IVCC(on)VCC current, enabledVSENSE = 2 V58mA
UNDERVOLTAGE LOCKOUT (UVLO)
VCCONVCC turn-on thresholdVCC rising11.512.613.5V
VCCOFFVCC turn-off thresholdVCC falling9.510.3511.5
UVLO Hysteresis1.852.152.45
REFERENCE
VREFVREF output voltage, no loadIVREF = 0 mA5.826.006.18V
VREF change with load0 mA ≤ IVREF ≤ −2 mA−1−6mV
VREF change with VCC12 V ≤ VCC ≤ 20 V210
ERROR AMPLIFIER
VSENSEreg25VSENSE input regulation voltageTA = 25 °C5.8566.15V
VSENSEregVSENSE input regulation voltage5.8266.18
IVSENSEVSENSE input bias currentIn regulation50100150nA
VENABVSENSE enable threshold, rising1.151.251.35V
VSENSE enable hysteresis0.020.070.15
VCOMPCLMPCOMP high voltage, clampedVSENSE = VSENSEreg – 0.3 V4.704.955.10
COMP low voltage, saturatedVSENSE = VSENSEreg + 0.3 V0.030.125
gMVSENSE to COMP transconductance, small signal0.99(VSENSEreg) < VSENSE < 1.01(VSENSEreg), COMP = 3 V405570µS
VSENSE high-going threshold to enable COMP large signal gain, percentRelative to VSENSEreg, COMP = 3 V3.25%5%6.75%
VSENSE low-going threshold to enable COMP large signal gain, percentRelative to VSENSEreg, COMP = 3 V−3.25%−5%−6.75%
VSENSE to COMP transconductance, large signalVSENSE = VSENSEreg – 0.4 V ,
COMP = 3 V
210290370µS
VSENSE to COMP transconductance, large signalVSENSE = VSENSEreg + 0.4 V,
COMP = 3 V
210290370
COMP maximum source currentVSENSE = 5 V, COMP = 3 V−80−125−170µA
RCOMPDCHGCOMP discharge resistanceHVSEN = 5.2 V, COMP = 3 V1.622.4
IDODCHGCOMP discharge current during DropoutVSENSE = 5 V, VINAC = 0.3 V3.244.8µA
VLOW_OVVSENSE over-voltage threshold, risingRelative to VSENSEreg7%8%10%
VSENSE over-voltage hysteresisRelative to VLOW_OV−1.5%−2%−3%
VHIGH_OVVSENSE 2nd over-voltage threshold, risingRelative to VSENSEreg10.5%11.3%14%
SOFT START
VSSTHRCOMP Soft-Start threshold, fallingVSENSE = 1.5 V152330mV
ISS,FASTCOMP Soft-Start current, fastSS-state, VENAB < VSENSE < VREF/2−80−125−170µA
ISS,SLOWCOMP Soft-Start current, slowSS-state, VREF/2 < VSENSE < 0.88VREF−11.5−16−20
KEOSSVSENSE End-of-Soft-Start threshold factorPercent of VSENSEreg96.5%98.3%99.8%
OUTPUT MONITORING
VPWMCNTLHVSEN threshold to PWMCNTLHVSEN rising2.352.502.65V
IHVSENHVSEN input bias current, highHVSEN = 3 V±0.03±0.5µA
IHV_HYSHVSEN hysteresis bias current, lowHVSEN = 2 V9.211.414
VHV_OV_FLTHVSEN threshold to over-voltage faultHVSEN rising4.644.875.1V
VHV_OV_CLRHVSEN threshold to over-voltage clearHVSEN falling4.454.674.8
VCOMP_PHFOFFPhase Fail monitoring-disable thresholdCOMP falling0.210.2250.25
VCOMP_PHFHYSPhase Fail monitoring hysteresisCOMP rising0.051
PWMCNTL output voltage lowHVSEN = 3 V, IPWMCNTL = 5 mA,
COMP = 0 V
0.20.5
tPHFDLYPhase Fail filter time to PWMCNTL highPHB = 5 V, ZCDA switching,
ZCDB = 0.5 V, COMP = 3 V
7.91217ms
IPWMCNTL_LEAKPWMCNTL leakage current, highHVSEN = 2 V, PWMCNTL = 15 V±0.03±0.5µA
GATE DRIVE(2)
GDA, GDB output voltage, highIGDA, IGDB = −100 mA11.512.415V
GDA, GDB on-resistance, highIGDA, IGDB = −100 mA8.814Ω
GDA, GDB output voltage, lowIGDA, IGDB = 100 mA0.180.32V
GDA, GDB on-resistance, lowIGDA, IGDB = 100 mA23.2Ω
GDA, GDB output voltage high, clampedVCC = 20 V, IGDA, IGDB = −5 mA1213.515V
GDA, GDB output voltage high, low VCCVCC = 12 V, IGDA, IGDB = −5 mA1010.511.5
Rise time1 V to 9 V, CLOAD = 1 nF1830ns
Fall time9 V to 1 V, CLOAD = 1 nF1225
GDA, GDB output voltage, UVLOVCC = 3.0 V, IGDA, IGDB = 2.5 mA100200mV
ZERO CURRENT DETECTOR
ZCDA, ZCDB voltage threshold, falling0.811.2V
ZCDA, ZCDB voltage threshold, rising1.51.71.9
ZCDA, ZCDB clamp, highIZCDA = +2 mA, IZCDB = +2 mA2.633.4
ZCDA, ZCDB clamp, lowIZCDA = −2 mA, IZCDB = −2 mA0−0.2−0.4
ZCDA, ZCDB input bias currentZCDA = 1.4 V, ZCDB = 1.4 V±0.03±0.5µA
ZCDA, ZCDB delay to GDA, GDB outputs(2)From ZCDx input falling to 1 V to respective gate drive output rising 10%50100ns
ZCDA blanking time(3)From GDA rising and GDA falling100
ZCDB blanking time(3)From GDB rising and GDB falling100
CURRENT SENSE
CS input bias current, dual-phaseAt rising threshold−120−166−200µA
CS current-limit rising threshold, dual-phasePHB = 5 V−0.18−0.2−0.22V
CS current-limit rising threshold, single-phasePHB = 0 V−0.149−0.166−0.183
CS current-limit reset falling threshold−0.003–0.015−0.025
CS current-limit response time(2)From CS exceeding threshold−0.05 V to GDx dropping 10%60100ns
CS blanking timeFrom GDx rising and falling edges100
VINAC INPUT
IVINACVINAC input bias current, above brownoutVINAC = 2 V±0.03±0.5µA
VBODETVINAC brownout detection thresholdVINAC falling1.331.391.44V
tBODLYVINAC brownout filter timeVINAC below the brownout detection threshold for the brownout filter time340440540ms
VBOHYSVINAC brownout threshold hysteresisVINAC rising306275mV
IBOHYSVINAC brownout hysteresis currentVINAC = 1 V for > tBODLY1.622.5µA
VDODETVINAC dropout detection thresholdVINAC falling0.3150.350.38V
tDODLYVINAC dropout filter timeVINAC below the dropout detection threshold for the dropout filter time3.557ms
VDOCLRVINAC dropout clear thresholdVINAC rising0.670.710.75V
PULSE-WIDTH MODULATOR
KTOn-time factor, phases A and BVSENSE = 5.8 V(4)3.64.04.4µs/V
KTSOn-time factor, single-phase, AVSENSE = 5.8 V, PHB = 0 V(4)7.28.08.9
Phase B to phase A on-time matching errorVSENSE = 5.8 V±2%±6%
Zero-crossing distortion correction additional on timeCOMP = 0.25 V, VINAC = 1 V1.222.8µs
COMP = 0.25 V, VINAC = 0.1 V12.62029
VPHBFPHB threshold falling, to single-phase operationTo GDB output shutdown, VINAC = 1.5 V0.70.80.9V
VPHBRPHB threshold rising, to two-phase operationTo GDB output running, VINAC = 1.5 V0.911.1
TMINMinimum switching periodRTSET = 133 kΩ(4)1.72.23µs
TSTARTPWM restart timeZCDA = ZCDB = 2 V(5)165210265
THERMAL SHUTDOWN
TJThermal shutdown temperatureTemperature rising(6)160°C
TJThermal restart temperatureTemperature falling(6)140
Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply. If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended. See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.
Refer to Figure 6-13, Figure 6-14, Figure 6-15, and Figure 6-16 of the Typical Characteristics for typical gate drive waveforms.
ZCD blanking times are ensured by design.
Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.
An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating temperature is not specified or assured.