The UCC28070A has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling either the GDA or GDB output whenever the corresponding current-sense input (CSA or CSB, respectively) rises above the voltage established on the PKLMT pin. Once an output has been disabled through the detection of peak current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming range of the PKLMT voltage extends to upwards of 4V to permit the full use of the 3V average current sense signal range; however, note that the linearity of the current amplifiers begins to compress above 3.6V.

A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT, provided the total current out of VREF is less than 2mA to avoid drooping of the 6V VREF voltage. TI recommends a load of less than 0.5mA, but if the resistance on PKLMT is very high, TI recommends a small filter capacitor on PKLMT to avoid operational problems in high-noise environments.

Figure 6-3 Externally Programmable Peak Current Limit

Peak Current Limit is a protection feature and has no built-in slope-compensation for duty-cycles greater than 0.5. During occurrences of peak limiting, sub-harmonic oscillation will occur with possible audible noise from such oscillation. If the PKLMT feature is re-purposed to implement a steady-state power-limit function, suitable slope compensation should be added by external means.