The outer voltage control loop of the dual-phase PFC controller functions the same as with a single-phase controller, and compensation techniques for loop stability are standard [7]. The bandwidth of the voltage-loop must be considerably lower than the twice-line ripple frequency (f_2LF) on the output capacitor to avoid distortion-causing correction to the output voltage. The output of the voltage-error amplifier (V_VAO) is an input to the multiplier to adjust the input current amplitude relative to the required output power. Variations on VAO within the bandwidth of the current loops influences the wave-shape of the input current. Because the low-frequency ripple on C_OUT is a function of input power only, its peak-to-peak amplitude is the same at high-line as at low-line. Any response of the voltage-loop to this ripple has a greater distorting effect on high-line current than on low-line current. Therefore, the allowable percentage of 3rd-harmonic distortion on the input current contributed by VAO must be determined using high-line conditions.

Because the voltage-error amplifier (VA) is a transconductance type of amplifier, the impedance on its input has no bearing on the amplifier gain, which is determined solely by the product of its transconductance (g_mv) with its output impedance (Z_OV). Thus, the VSENSE input divider-network values are determined separately based on criteria discussed in VSENSE and VINAC Open-Circuit Protection. Its output is the VAO pin.

Figure 6-6 Voltage Error Amplifier With Type II Compensation

The twice-line ripple voltage component of V_VSENSE must be sufficiently attenuated and phase-shifted at VAO to achieve the desired level of 3rd-harmonic distortion of the input current wave-shape [4]. For every 1% of 3rd-harmonic input distortion allowable, the small-signal gain G_VEA = V_VAOpk / v_SENSEpk = g_mv × Z_OV at the twice-line frequency must allow no more than 2% ripple over the full V_VAO voltage range. In the UCC28070A, V_VAO can range from 1V at zero load power to approximately 4.2V at full load power for a ΔV_VAO = 3.2V, so 2% of 3.2V is 64mV peak ripple.

The output capacitor maximum low-frequency, zero-to-peak, ripple voltage is closely approximated by:

Equation 28.

where:

• P_IN(avg) is the total maximum input power of the interleaved-PFC preregulator
• V_OUT(avg) is the average output voltage
• C_OUT is the output capacitance

where

• k_R is the gain of the resistor-divider network on VSENSE

Thus, for k_3rd, the percentage of allowable 3rd-harmonic distortion on the input current attributable to the VAO ripple,

Equation 30.

This impedance on VAO is set by a capacitor (C_PV), where C_PV = 1 / (2πf_2LF × Z_OV(f_2LF)); therefore:

Equation 31.

The voltage-loop unity-gain cross-over frequency (f_VXO) may now be solved by setting the open-loop voltage transfer function gain equal to 1:

Equation 32.

Equation 33. so,

The zero-resistor (R_ZV) from the zero-placement network of the compensation may now be calculated. Together with C_PV, R_ZV sets a pole right at f_VXO to obtain 45° phase margin at the cross-over.

Equation 34. Thus,

Finally, a zero is placed at or below f_VXO / 6 with capacitor C_ZV to provide high gain at DC but with a breakpoint far enough below f_VXO so as not to significantly reduce the phase margin. Choosing f_VXO / 10 allows one to approximate the parallel combination value of C_ZV and C_PV as C_ZV, and solve for C_ZV simply as:

Equation 35.

By using a spreadsheet or math program, C_ZV, R_ZV, and C_PV may be manipulated to observe their effects on f_VXO and phase margin and the percentage contribution to 3rd-harmonic distortion. Also, phase margin may be checked as P_IN(avg) level and system parameter tolerances vary.