SLUSAW0B March   2012  – December 2023 UCC28070A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Voltage Biasing (VCC and VVREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.14 Adaptive Soft Start

To maintain a controlled power up, the UCC28070A has been designed with an adaptive soft-start function that overrides the internal reference voltage with a controlled voltage ramp during power up. On initial power up, once VVSENSE exceeds the 0.75V enable threshold (VEN), the internal pulldown on the SS pin is released, and the 1.5mA adaptive soft-start current source is activated. This 1.5mA pullup almost immediately pulls the SS pin to 0.75V (VVSENSE) to bypass the initial 25% of dead time during a traditional 0V to VREGULATION SS ramp. Once the SS pin has reached the voltage on VSENSE, the 10μA soft-start current (ISS) takes over. Thus, through the selection of the soft-start capacitor (CSS), the effective soft-start time (tSS) may be easily programmed based on Equation 21.

Equation 21. GUID-507C8B1B-4A27-4024-8D2B-5AE0B8D29808-low.gif

Often, a system restart is desired following a brief shutdown. In such a case, VSENSE may still have substantial voltage if VOUT has not fully discharged or if high line has peak charged COUT. To eliminate the delay caused by charging CSS from 0V up to the precharged VVSENSE with only the 10μA current source and minimize any further output voltage sag, the adaptive soft start uses a 1.5mA current source to rapidly charge CSS to VVSENSE, after which time the 10μA source controls the VSS rise at the desired soft-start ramp rate. In such a case, tSS is estimated as follows:

Equation 22. GUID-5A70E983-BE57-4CCA-94BC-DBFACF7945C0-low.gif

where

  • VVSENSE0 is the voltage at VSENSE at the moment a soft start or restart is initiated
Note:

For soft start to be effective and avoid overshoot on VOUT, the SS ramp must be slower than the voltage-loop control response. Choose CSS ≥ CVZ to ensure this.

GUID-E9943C30-0281-42CF-BA95-CD538AE658D1-low.gif Figure 6-4 Soft-Start Ramp Rate