Table 1. Design Parameters

8.2.2.1 Power Stage

8.2.2.1.1 L_BOOST

The boost inductor value is determined by:

Equation 7.

where

• D is the duty cycle
• ΔI is the inductor ripple current
• f_S is the switching frequency

For the example circuit in Figure 9, a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688, and a minimum input voltage of 85 V_RMS give a boost inductor value of approximately 1 mH. The values used in this equation are at the peak of low line, where the inductor current and its ripple are at a maximum.

8.2.2.1.2 C_OUT

Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For the circuit in Figure 9, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output power, output voltage, and holdup time gives the equation:

Equation 8.

In practice, the calculated minimum capacitor value may be inadequate, because output ripple voltage specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often requires the use of a much larger capacitor value than calculated. The amount of output capacitor ESR allowed is determined by dividing the maximum specified output ripple voltage by the inductor ripple current. In the design in Figure 9, holdup time is the dominant determining factor, and a 220-μF, 450-V capacitor was chosen for the output voltage level of 385 VDC at 250 W.

8.2.2.2 Softstart

The softstart circuitry prevents overshoot of the output voltage during start up by bringing up the voltage amplifier output (V_VAOUT) slowly, which allows for the PWM duty cycle to increase slowly. Use the following equation to select a capacitor for the softstart pin.

In this example, t_DELAY is equal to 7.5 ms, which would yield a C_SS of 10 nF.

Equation 9.

In an open-loop test circuit, shorting the softstart pin to ground does not ensure 0% duty cycle. This is due to the input offset voltage of the current amplifier, which could force the current amplifier output high or low depending on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and bias current to overcome the offset voltage of the current amplifier.

8.2.2.3 Multiplier

The output of the multiplier of the UCC3817 is a signal representing the desired input line current. The multiplier is an input to the current amplifier, which programs the current loop to control the input current to give high power factor operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the multiplier are VAOUT, the voltage amplifier error signal, I_IAC, a representation of the input rectified ac line voltage, and an input voltage feedforward signal, V_VFF. The output of the multiplier, I_MOUT, can be expressed as:

Equation 10.

where

• K is a constant typically equal to 1/V

Electrical Characteristics covers all the required operating conditions for designing with the multiplier. Additionally, Figure 3, Figure 4, and Figure 5 provide typical multiplier characteristics over its entire operating range.

The I_IAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin of the UCC381x. This resistor (R_IAC) is sized to give the maximum I_IAC current at high line. For the UCC381x, the maximum I_IAC current is approximately 500 μA. A higher current than this can drive the multiplier out of its linear range. A smaller current level is functional, but noise can become an issue, especially at low input line. Assuming a universal line operation of 85 V_RMS to 265 V_RMS gives an R_IAC value of 750 kΩ. Because of voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors connected in series to give the required resistance and distribute the high voltage amongst the resistors. For the design example in Figure 9, two 383-kΩ resistors are used in series.

The current into the IAC pin is mirrored internally to the VFF pin, where it is filtered to produce a voltage feed forward signal proportional to line voltage. The VFF voltage keeps the power stage gain constant, and to provide input power limiting. Refer to Texas Instruments application note DN-66 UC3854A/B and UC3855A/B Provide Power Limiting with Sinusoidal Input (SLUA196) for detailed explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF resistor (R_VFF) to provide power limiting where V_IN(min) is the minimum RMS input voltage, and R_IAC is the total resistance connected between the IAC pin and the rectified line voltage.

Equation 11.

Because the VFF voltage is generated from line voltage, it must be adequately filtered to reduce total harmonic distortion caused by the 120-Hz rectified line voltage. Refer to Unitrode Power Supply Design Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter is adequate for the design in Figure 9. Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second harmonic ripple is 66% of the input AC line voltage, the amount of attenuation required by this filter is:

1.5%/66% = 0.022

With a ripple frequency (f_R) of 120 Hz and an attenuation of 0.022, the pole of the filter (f_P) must be placed at:

The following equation can be used to select the filter capacitor (C_VFF) required to produce the desired low pass filter.

The R_MOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier current. The maximum multiplier current, or I_MOUT(max), is determined by the equation:

Equation 14.

I_MOUT(max) for the design in Figure 9 is approximately 315 μA. The R_MOUT resistor is then determined by:

In this example, V_RSENSE is selected to give a dynamic operating range of 1.25 V, which gives an R_MOUT of approximately 3.91 kΩ.

8.2.2.4 Voltage Loop

The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. This ripple is fed back through the error amplifier, and appears as a 3rd-harmonic ripple at the input to the multiplier. The voltage loop must be compensated, not just for stability, but also to attenuate the contribution of this ripple to the total harmonic distortion of the system (refer to Figure 10).

Figure 10. Voltage Amplifier Configuration

The gain of the voltage amplifier, G_VA, is determined by first calculating the amount of ripple present on the output capacitor. The peak value of the second harmonic voltage is given by the equation:

In this example, V_OPK is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from the voltage loop to the total harmonic distortion budget, set the gain equal to:

The network must realize this filter is comprised of an input resistor, R_IN, and feedback components C_f, C_Z, and R_f. The value of R_IN is already determined, because of its function as one half of a resistor divider from V_OUT feeding back to the voltage amplifier for output voltage regulation. In this case, the value was chosen to be 1 MΩ. This high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be realized by the use of two 500-kΩ resistors in series, because of the voltage rating constraints of most standard 1/4-W resistors. The value of C_f is determined by the equation:

In this example, C_f equals 150 nF. Resistor R_f sets the dc gain of the error amplifier and thus determines the frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop equation to one, and solving for the crossover frequency. The frequency, expressed in terms of input power, can be calculated by the equation:

f_VI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design Seminar SEM1000, Topic 1, [A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage Transitions].

Solving for R_f becomes:

or R_f equals 100 kΩ.

Due to the low output impedance of the voltage amplifier, capacitor C_Z was added in series with R_F to reduce loading on the voltage divider. To ensure the voltage loop crossed over at f_VI, C_Z was selected to add a zero at a 10th of f_VI. For the design in Figure 9, a 2.2-μF capacitor was chosen for C_Z. The following equation can calculate C_Z.

Equation 21.

8.2.2.5 Current Loop

The gain of the power stage is:

R_SENSE has been chosen to give the desired differential voltage for the current sense amplifier at the desired current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amp of 1 V gives a R_SENSE value of 0.25 Ω. V_P in this equation is the voltage swing of the oscillator ramp, 4 V for the UCC3817. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz, requires a power stage gain at that frequency of 0.383. For the system to have a gain of 1 at the crossover frequency, the current amplifier must have a gain of 1/G_ID at that frequency. G_EA, the current amplifier gain is then:

R_I is the R_MOUT resistor, previously calculated to be 3.9 kΩ. (refer to Figure 11). The gain of the current amplifier is R_f/R_I, so multiplying R_I by G_EA gives the value of R_f,which in this case is approximately 12 kΩ. Setting a zero at the crossover frequency and a pole at half the switching frequency completes the current loop compensation.

Figure 11. Current Loop Compensation

The UCC3817 current amplifier has the input from the multiplier applied to the inverting input. This change in architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier and adds a phase inversion into the control loop. The UCC3817 takes advantage of this phase inversion to implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and cost and reducing EMI. This is explained in greater detail in Capacitor Ripple Reduction. The UCC3817 current amplifier configuration is shown in Figure 12.

Figure 12. UCC3817 Current Amplifier Configuration

8.2.2.6 Start Up

The UCC3818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC3817 has an internal shunt regulator, enabling the device to be powered from bootstrap circuitry as shown in Figure 9. The current drawn by the UCC3817 during undervoltage lockout, or start-up current, is typically 150 μA. Once VCC is above the UVLO threshold, the device is enabled and draws 4 mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides the VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system design.

Assuming a 1 second allowed start-up time, a 16-V VCC turn-on threshold, and a total VCC capacitance of 100 μF, a resistor value of 51 kΩ is required at a low line input voltage of 85 V_RMS. The IC start-up current is sufficiently small as to be ignored in sizing the start-up resistor.