Refer to the PDF data sheet for device specific package drawings
The UCC28600 is a PWM controller with advanced energy features to meet stringent world-wide energy efficiency requirements.
UCC28600 integrates built-in advanced energy saving features with high-level protection features to provide cost-effective solutions for energy-efficient power supplies. UCC28600 incorporates frequency fold-back and green-mode operation to reduce the switching losses at light-load and no-load conditions.
UCC28600 is available in the 8-pin SOIC package. Operating junction temperature range is –40°C to +105°C.
The UCC28600 Design Calculator, (SLVC104), located in the Tools and Software section of the UCC28600 product folder, provides a user-interactive iterative process for selecting recommended component values for an optimal design.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC28600 | SOIC (8) | 4.90 mm × 3.91 mm |
Changes from J Revision (July 2011) to K Revision
Changes from H Revision (November 2005) to I Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CS | 3 | I | Current sense input. Also programs power limit, and used to control modulation and activate overcurrent protection. The CS voltage input originates across a current sense resistor and ground. Power limit is programmed with an effective series resistance between this pin and the current sense resistor. |
FB | 2 | I | Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated voltage. Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the emitter of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the three modes: quasi resonant (QR), frequency foldback mode (FFM) and green mode (GM). |
GND | 4 | – | Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the capacitor as close to these two pins as possible. |
OUT | 5 | O | 1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and switches between GND and the lower of VDD or the 13-V internal output clamp. |
OVP | 7 | I | Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on. Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity with resistors connected to this pin. |
SS | 1 | I | Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the capacitance and the internal soft-start charge current. The soft-start capacitor should be placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge the SS pin to GND through an internal MOSFET with an RDS(on) of approximately 100 Ω. The internal modulator comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit. |
STATUS | 8 | O | ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to disable the PFC control circuit (high impedance = green mode). STATUS pin is high during UVLO, (VDD < start-up threshold), and softstart, (SS < FB). |
VDD | 6 | I | Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND. |