SLUS646K November   2005  – August 2015 UCC28600

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 Terminal Components
    3. 7.3 Feature Description
      1. 7.3.1 Oscillator
      2. 7.3.2 Status
      3. 7.3.3 Fault Logic
      4. 7.3.4 Protection Features
      5. 7.3.5 Overtemperature
      6. 7.3.6 Cycle-by-Cycle Power Limit
      7. 7.3.7 Primary Current Protection
      8. 7.3.8 Over-Voltage Protection
      9. 7.3.9 Undervoltage Lockout
    4. 7.4 Device Functional Modes
      1. 7.4.1 Quasi-Resonant and DCM Control
      2. 7.4.2 Frequency Foldback Mode Control
      3. 7.4.3 Green-Mode Control
      4. 7.4.4 Operating Mode Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitor and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Turns Ratio and Primary Inductance
        3. 8.2.2.3 Non-Ideal Current Sense Value
        4. 8.2.2.4 Snubber Damping
        5. 8.2.2.5 Open Loop Test Circuit
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Related Products
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

To increase the reliability and feasibility of the design it is recommended to adhere to the following guidelines for PCB layout. 

  1. Minimize the high current loops to reduce parasitic capacitances and inductances.  At the same time, do not inadvertently make traces with a high dv/dt too wide as this will create a very good E-field antenna.
  2. Separate the device signal ground from the high current power ground in order to isolate the noise away from the device substrate.  The separate grounds should, ideally, be tied together at the input capacitor on the primary side.
  3. Return the sense resistor to the ground side of the input capacitor, instead of to the ground plane under the device.
  4. The bypass capacitor on VDD must be placed as close as possible to the VDD and GND pins of the device.
  5. The filter capacitor on CS must be placed as close as possible to the CS pin and GND pin of the device.
  6. The filter capacitor on FB must be placed as close as possible to the FB and GND pins of the device.

10.2 Layout Example

The partial layout example shown in Figure 25 demonstrates an effective component and track arrangement for the printed circuit board. Actual board layout must conform to the constraints on a specific design, so many variations are possible.

UCC28600 layout_lus646.gifFigure 25. Partial Layout Example Showing Component Placement