8.3.4 Magnetic Input and Output Voltage Sensing

A sense winding on the transformer is used to measure the input voltage and output voltage of the power stage. This winding is typically the converter bias winding. The sense winding should be interfaced to the VSENSE pin as shown in Figure 21. This interface requires that the voltage across the winding be scaled with a resistor divider R_A / R_B, and then offset with a switched, pull-up resistor R_P (in series with a diode) connected to the gate drive pin DRV.

Figure 21. VSENSE Pin Interface Arrangement

During the off-time portion of the switching cycle (also referred to as the flyback interval), the resistor divider (R_B / (R_A + R_B)) scales the positive voltage swing at the VSENSE pin for output voltage regulation, as shown in Figure 22. During this interval, since the DRV output is low, the diode in series with R_P is reverse-biased, and so R_P is out-of-circuit.

Figure 22. V_OUT Sense Using the Positive Swing on the Sense Winding

During the on-time portion of the switching cycle, when the DRV pin goes high (should swing very close to the value at the VDD pin), the switched pull-up R_P allows the negative swing on the winding to be level-shifted positive, and thus also be sensed at the VSENSE pin, as shown in Figure 23. In this way the bias winding may be used to sense both line input voltage and output voltage.

Uses of the sensed bulk and output voltages:

• Input AC mains UVLO
• Input brownout
• Line-dependent peak-current adjustment
• Accurate output-current regulation
• Output-voltage regulation
• Output over-voltage protection (OVP)

Figure 23. Line Input Sense by Offsetting the Negative Swing on the Sense Winding

In order to protect the VSENSE pin from excessive negative current in the event of a manufacturing fault (such as an open circuit on R_P), use a series limiting resistor and clamping diode on the VSENSE pin. Combine the clamping diode and DRV pull-up diode into a single-package common-cathode diode to reduce the component count of the system. This is illustrated in Figure 24.

Figure 24. VSENSE Pin Protection and Interface to Bias Winding

The device continually adjusts the input voltage sample delay, measuring the sample half-way through the on-time interval, to ensure the cleanest signal. The device uses same mid-point sample trigger when measuring the main MOSFET switch current (I_SW). Sampling MOSFET switch current in the middle of the on-time automatically measures the average current during the on-time, I_{SW(on_avg)}, which is required for the current limit and overload timer block.

The output voltage sample point is always time relative to the turn-off instant. Internally, the device uses the CS pin to determine the cycle end, rather than the PWM falling edge on the DRV pin. The device bases this determination on the instant that the MOSFET switch current drops below the demanded peak current level (I_PEAK ) at the peak current mode comparator. Some delay always occurs from the falling edge on DRV to the point when the external power MOSFET turns off. This internal timing method ensures a more accurate measure of I_{SW(on_avg)}, and also ensures that the output voltage sample point is not measured too early, before the leakage ringing has subsided. The effect of the gate turn-off delay and the adjustment of the output voltage sample point is illustrated in Figure 25.

Figure 25. V_OUT Sample Adjust for External Gate Delay

The sampling of the input voltage and output voltage signals on the bias winding must be synchronized to the on-time and off-time flyback intervals respectively, because the signals occur during only those intervals in the switching cycle. Typical waveforms and timing are illustrated in Figure 26.

More conventional knee-point detection schemes, where the sample is measured at the end of the flyback interval when the secondary-side current has decayed to zero, inherently always operate in discontinuous conduction mode (DCM). However, the fixed sample-point scheme used on the UCC2863x has the advantages of being able to operate in regions of fixed frequency, and being able to operate in continuous conduction mode (CCM). Fixed sample-point schemes conventionally suffer poorer regulation than knee-point schemes, because there is always current flowing at the sample instant. This current produces a sensing error as a result of the voltage drop produced across the secondary-side resistance and leakage inductance. This parasitic voltage drop varies with output voltage, line and load, thus influencing the regulation. The UCC2863x devices uses a novel internal compensation scheme to adjust for this parasitic voltage drop, and can deliver excellent static line and load regulation, even when operating heavily in CCM.

Figure 26. V_IN and V_OUT Sample Trigger Timing