8.3.20 External Wake Input at VSENSE Pin (UCC28633 Only)

The UCC28633 device variant supports fast PSR transient response via the VSENSE pin. When the loop demand drives the modulator frequency below approximately f_SMP(max), the controller enters a low-power sleep mode for a portion of the switching cycle. The sleep interval varies, depending on the switching frequency commanded. The sleep interval is longer for lower switching frequency, and longest at f_SW(min). For conventional PSR controllers, if a load transient occurs during this sleep interval, the controller will not react until the next timed wake-up, during which the output voltage can drop significantly, depending on the size of the load step and the amount of output capacitance.

The UCC28633 can respond to fast transient wake signal coupled to the VSENSE pin. If the wake signal exceeds an internal pin threshold V_SENSE(wake) while the controller is in sleep mode, the sleep interval is terminated and PWM activity commences within a typical delay time of t_WAKE. This dramatically improves the response to heavy load transients from zero load, or very light load. If the switching frequency is above f_SMP(max), the controller never enters sleep mode, so wake response on the VSENSE pin never enabled. The commencement of any sleep interval in the controller is delayed until the resonant ringing on the VENSE pin has decreased below the V_SENSE(wake) threshold for at least 2 µs. Once the ringing has decreased, the wake response is enabled, and the sleep interval commences.

Figure 39. UCC24650 Secondary-Side Voltage Monitor and Wake-Up Circuit

The wake signal at the VSENSE pin can be generated using a secondary side low power voltage monitor such as UCC24650, as shown in Figure 39. Further details can be found in the datasheet for UCC24650. This secondary-side monitor uses the switching activity on the secondary winding to trigger refresh of an internal sample-and-hold circuit to measure and record the system output voltage at the VDD pin. Thereafter, if the actual output voltage, sensed at the VDD pin, drops by ΔWAKE% (see UCC24650 detailed datasheet specifications) of the previously sampled value, the WAKE pin is internally pulled low through a current-limited open-drain switch. As shown in Figure 39, the main output rectifier diode is positioned at the return side of the secondary winding, so that the GND-referenced UCC24650 WAKE function can be deployed. In effect, the WAKE pin shorts out the rectifier diode for a short interval (see UCC24650 detailed datasheet specifications), to draw some current from the output capacitor through the transformer secondary winding. This sets up a low-level pulse of current that then rings resonantly in the power circuit magnetizing inductance and parasitic capacitance. The ringing causes a similar ringing voltage waveform on all transformer windings, including the bias/sense winding, which interfaces to the VSENSE pin. If the initial pulse of current drawn by the secondary WAKE pin is sufficient, then the ringing voltage at the VSENSE pin is large enough to exceed the V_SENSE(wake) threshold.

The UCC24650 datasheet Application Information section includes details of how to estimate the amplitude of the wake-pulse ringing at the WAKE pin. In some cases, especially at higher rated output power, the transformer magnetizing inductance is lower, while the total switch node capacitance tends to be higher. This reduces the transformer impedance, and can also result in reduced wake pulse amplitude. In these cases, the UCC24650 WAKE pin output can be augmented with an external PNP circuit Q1, R1 and R2, as shown in Figure 40. In this case, when the WAKE pin pulls low, Q1 turns on, and draws more current through the secondary winding. A current limiting resistor R1 is recommended in series with either collector or emitter. Effectively R1 swamps the UCC24650 internal WAKE pin resistance, R_WAKE. A pull-up resistor R2 from base to emitter is also required, to ensure that the WAKE pin is adequately pulled up/down during normal switching activity to properly trigger the internal sample and hold on the VDD pin. The external PNP device Q1 must have at least the same voltage rating as the main rectifier diode.

Figure 40. Augmented UCC24650 Secondary-Side Voltage Monitor and Wake-Up Circuit