SLUSCR9B June   2017  – December 2020 UCC28730-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 HV (High Voltage Startup)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CBC (Cable Compensation)
        6. 7.3.1.6 VS (Voltage Sense)
        7. 7.3.1.7 CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-By Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CVDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1  Capacitance Terms in Farads
        2. 11.1.1.2  Duty-Cycle Terms
        3. 11.1.1.3  Frequency Terms in Hertz
        4. 11.1.1.4  Current Terms in Amperes
        5. 11.1.1.5  Current and Voltage Scaling Terms
        6. 11.1.1.6  Transformer Terms
        7. 11.1.1.7  Power Terms in Watts
        8. 11.1.1.8  Resistance Terms in Ω
        9. 11.1.1.9  Timing Terms in Seconds
        10. 11.1.1.10 DC Voltage Terms in Volts
        11. 11.1.1.11 AC Voltage Terms in Volts
        12. 11.1.1.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONMINTYPMAXUNIT
HIGH-VOLTAGE START-UP
IHVStart-up current out of VDDVHV = 100 V, VVDD = 0 V, start state100250500µA
VHV = 30 V, VVDD = VVDD(on)–0.5 V, start state 100 410
IHVLKG25Leakage current into HVVHV = 400 V, run state, TJ = 25°C0.010.5µA
BIAS SUPPLY INPUT CURRENT
IRUNSupply current, runRun state, IDRV = 0 A2.12.65mA
IWAITSupply current, waitWait state, IDRV = 0 A, VVDD = 20 V5275µA
ISTARTSupply current, startStart state, IDRV = 0 A, VVDD = 18 V, IHV = 0 A1830µA
IFAULTSupply current, faultFault state, IDRV = 0 A5475µA
UNDER-VOLTAGE LOCKOUT
VVDD(on)VDD turn-on thresholdVVDD low to high17.52123V
VVDD(off)VDD turn-off thresholdVVDD high to low7.37.78.1V
VS Input and Wake-Up Monitor
VVSRRegulating level(1)Measured at no-load condition,  TJ = 25°C4.004.044.08V(1)
VVSNCNegative clamp level below GNDIVSLS = –300 µA190250325mV
IVSBInput bias currentVVS = 4 V–0.2500.25µA
VWU(high)Wake-up threshold at VS, high(2)VS pin rising2V(2)
VWU(low)Wake-up threshold at VS, lowVS pin rising1557105mV
CS INPUT
VCST(max)CS maximum threshold voltage(3)VVS = 3.7 V710740770mV(3)
VCST(min)CS minimum threshold voltageVVS = 4.35 V230249270mV
KAMAM control ratio, VCST(max) / VCST(min)2.752.993.20V/V
VCCRConstant-current regulation factor310319329mV
KLCLine compensation current ratio, IVSLS / current out of CS pinIVSLS = –300 µA2425.328A/A
DRIVER
IDRSDRV source currentVDRV = 8 V, VVDD = 9 V202935mA
RDRVLSDRV low-side drive resistanceIDRV = 10 mA612Ω
VDRCLDRV clamp voltageVVDD = 35 V1314.516V
RDRVSSDRV pull-down in start state150190230kΩ
PROTECTION
VOVPOver-voltage threshold(1)At VS input, TJ = 25°C4.524.624.71V(1)
VOCPOver-current thresholdAt CS input1.41.51.6V
IVSL(run)VS line-sense run currentCurrent out of VS pin increasing190225275µA
IVSL(stop)VS line-sense stop currentCurrent out of VS pin decreasing7080100µA
KVSLVS line-sense ratio, IVSL(run) / IVSL(stop)2.452.83.05A/A
TJ(stop)Thermal shut-down temperatureInternal junction temperature165°C
CABLE COMPENSATION
VCBC(max)Cable compensation output maximum voltageVoltage at CBC at full load2.93.133.5V
VCVS(min)Minimum compensation at VSVCBC = open, change in VS regulating level from no load to full load–50–1520mV
VCVS(max)Maximum compensation at VSVCBC = 0 V, change in VS regulating level from no load to full load275325375mV
(1) The regulating level and OV threshold at VS decrease with increasing temperature by 1 mV/°C. This compensation over temperature is included to reduce the variances in power supply output regulation and over-voltage detection with respect to the external output rectifier.
(2) Designed for accuracy within ±10% of typical value.
(3) These threshold voltages represent average levels. This device automatically varies the current sense thresholds to improve EMI performance.