SLUSDT2C August   2019  – December 2020 UCC28740-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
      2. 7.3.2 Valley-Switching and Valley-Skipping
      3. 7.3.3 Startup Operation
      4. 7.3.4 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 7.4.2 Primary-Side Constant-Current (CC) Regulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 High Voltage Applications
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1  Custom Design With WEBENCH® Tools
        2. 8.3.2.2  Standby Power Estimate and No-Load Switching Frequency
        3. 8.3.2.3  Input Bulk Capacitance and Minimum Bulk Voltage
        4. 8.3.2.4  35
        5. 8.3.2.5  Transformer Turns-Ratio, Inductance, Primary Peak Current
        6. 8.3.2.6  Transformer Parameter Verification
        7. 8.3.2.7  VS Resistor Divider, Line Compensation
        8. 8.3.2.8  Output Capacitance
        9. 8.3.2.9  VDD Capacitance, CVDD
        10. 8.3.2.10 Feedback Network Biasing
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VDD Pin
      2. 10.1.2 VS Pin
      3. 10.1.3 FB Pin
      4. 10.1.4 GND Pin
      5. 10.1.5 CS Pin
      6. 10.1.6 DRV Pin
      7. 10.1.7 HV Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ohms
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in VRMS
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.6 Transformer Parameter Verification

Because the selected transformer turns-ratio affects the MOSFET VDS and the secondary and auxiliary rectifier reverse voltages, a review of these voltages is important. In addition, internal timing constraints of the UCC28740-Q1 require a minimum on time of the MOSFET (tON) and a minimum demagnetization time (tDM) of the transformer in the high-line minimum-load condition. The selection of fMAX, LP, and RCS affects the minimum tON and tDM.

Equation 19 and Equation 20 determine the reverse voltage stresses on the secondary and auxiliary rectifiers. Stray inductance can impress additional voltage spikes upon these stresses and snubbers may be necessary.

Equation 19. GUID-8876E7B9-89B7-4A16-9250-795003149538-low.gif
Equation 20. GUID-48FCAE44-1B62-4F68-9F5D-632F2E05ADC8-low.gif

For the MOSFET VDS peak voltage stress, an estimated leakage inductance voltage spike (VLK) is included.

Equation 21. GUID-00198252-02E2-451A-97B7-90EC9871E987-low.gif

Equation 22 determines if tON(min) exceeds the minimum tON target of 280 ns (maximum tCSLEB). Equation 23 verifies that tDM(min) exceeds the minimum tDM target of 1.2 µs.

Equation 22. GUID-B3EDC514-D931-45AF-810A-73F729BAB480-low.gif
Equation 23. GUID-542882B5-315E-49C1-8AE8-5F39F934F1A8-low.gif