The capacitance on VDD must supply the primary-side operating current used during startup and between low-frequency switching pulses. The largest result of three independent calculations denoted in Equation 28, Equation 29, and Equation 30 determines the value of C_VDD.

At startup, when V_VDD(on) is reached, C_VDD alone supplies the device operating current and MOSFET gate current until the output of the converter reaches the target minimum-operating voltage in CC regulation, V_OCC. Now the auxiliary winding sustains VDD for the UCC28740-Q1 above UVLO. The total output current available to the load and to charge the output capacitors is the CC-regulation target, I_OCC. Equation 28 assumes that all of the output current of the converter is available to charge the output capacitance until V_OCC is achieved. For typical applications, Equation 28 includes an estimated q_Gf_SW(max) of average gate-drive current and a 1-V margin added to V_VDD.

Equation 28.

During a worst-case un-load transient event from full-load to no-load, C_OUT overcharges above the normal regulation level for a duration of t_OV, until the output shunt-regulator loading is able to drain V_OUT back to regulation. During t_OV, the voltage feedback loop and optocoupler are saturated, driving maximum I_FB and temporarily switching at f_SW(min). The auxiliary bias current expended during this situation exceeds that normally required during the steady-state no-load condition. Equation 29 calculates the value of C_VDD (with a safety factor of 2) required to ride through the t_OV duration until steady-state no-load operation is achieved.

Equation 29.

Finally, in the steady-state no-load operating condition, total no-load auxiliary-bias current, I_AUXNL is provided by the converter switching at a no-load frequency, f_SWNL, which is generally higher than f_SW(min). C_VDD is calculated to maintain a target VDD ripple voltage lower than ΔV_VDD, using Equation 30.

Equation 30.