SLUSD71A April   2018  – May 2018 UCC28742

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Efficiency of a 10-W, 5-V AC-to-DC Converter
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 FB (Feedback)
      2. 7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      3. 7.3.3 Control Law
      4. 7.3.4 Constant Current Limit and Delayed Shutdown
      5. 7.3.5 Valley-Switching and Valley-Skipping
      6. 7.3.6 Start-Up Operation
      7. 7.3.7 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  VDD Capacitance, CDD
        3. 8.2.2.3  VDD Start-Up Resistance, RSTR
        4. 8.2.2.4  Input Bulk Capacitance and Minimum Bulk Voltage
        5. 8.2.2.5  Transformer Turns Ratio, Inductance, Primary-Peak Current
        6. 8.2.2.6  Transformer Parameter Verification
        7. 8.2.2.7  VS Resistor Divider and Line Compensation
        8. 8.2.2.8  Standby Power Estimate
        9. 8.2.2.9  Output Capacitance
        10. 8.2.2.10 Feedback Loop Design Consideration
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ω
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in VRMS
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Constant Current Limit and Delayed Shutdown

Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary constant current limit, CCL, thus to achieve load over-current protection. The control law dictates that as power is increased in CV regulation and approaching CCL the primary-peak current is at IPP(max). Referring to Figure 13 below, the primary peak current (IPP), turns-ratio (NS/NP), secondary demagnetization time (tDMAG), and switching period (tSW) determine the secondary average output current. Ignoring leakage inductance effects, the average output current is given by Equation 5. By regulating the secondary rectifier conduction duty cycle, the output current limit is achieved for given IPP and transformer turns-ratio. When the load increases, the secondary-side rectifier conduction duty cycle keep increasing. Once this duty cycle reaches preset value of 0.475, the converter switching frequency stops increasing and starts adjusting to reduce and maintain 0.475 secondary-side duty cycle. Therefore, the output constant current limit is achieved. Because the current is kept constant, the increasing load results in lower output voltage.

Equation 5. UCC28742 qu05_from_qu7_lusca8.gif
UCC28742 fig13_from_fig16_lusca8.gifFigure 13. Transformer Currents

As shown in Figure 14 below, CV mode operation is from IO = 0 to < IOCC; at IO = IOCC, the operation enters constant current limit mode and VO starts to drop as the load resistance becomes further lower while IO is maintained at IOCC for a time interval specified by tOVL_TIME typically 120 ms then DRV stops to achieve converter output delayed shutdown. During the 120-ms timing interval, if load IO reduces to < IOCC, the timer will be reset and no shutdown will occur. The V-I curve corresponding to the operation is shown in Figure 14, and the delayed shutdown timing diagram is shown in Figure 15. Note (1) The timer tOVL_TIME is triggered whenever IO reaches IOCC and reset when IO drops to < IOCC before 120ms-time-out. (2) during 120-ms time interval, when load resistance becomes so low during constant current interval that causes the device VDD to reach its VVDD(off) and then the shutdown will be through VDD undervoltage lockout instead of through Constant Current Limit and Delayed Shutdown. In such a case, the shutdown can happen before 120ms timer out.

UCC28742 fig14_OVL_cover_2.gifFigure 14. Typical Target Output V-I Characteristics
UCC28742 fig15.gifFigure 15. Output Delayed Shutdown Timing