SLUSD12A October   2017  – February 2018 UCC28780

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. 7.4.10.1 Brown-In and Brown-Out
        2. 7.4.10.2 Output Over-Voltage Protection
        3. 7.4.10.3 Over-Temperature Protection
        4. 7.4.10.4 Programmable Over-Power Protection
        5. 7.4.10.5 Peak Current Limit
        6. 7.4.10.6 Output Short-Circuit Protection
        7. 7.4.10.7 Over-Current Protection
        8. 7.4.10.8 Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. 7.4.11.1 Protections on CS pin Fault
        2. 7.4.11.2 Protections on HVG pin Fault
        3. 7.4.11.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Turns (NP)
          4. 8.2.2.2.4 Secondary Turns (NS)
          5. 8.2.2.2.5 Turns of Auxiliary Winding (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Clamp Capacitor Calculation
        4. 8.2.2.4 Bleed-Resistor Calculation
        5. 8.2.2.5 Output Filter Calculation
        6. 8.2.2.6 Calculation of ZVS Sensing Network
        7. 8.2.2.7 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Dead-Time Optimization

The dead-time optimizer in Figure 19 controls the two dead-times: the dead-time between PWMH falling edge and PWML rising edge (tZ), as well as the dead-time between PWML falling edge and PWMH rising edge (tD(PWML-H)).

The adaptive control law for tZ of UCC28780 utilizes the line feed-forward signal to extend tZ as VBULK reduces, as shown in Figure 21. The VS pin senses VBULK through the auxiliary winding voltage (VAUX) when the low-side switch (QL) is on. The auxiliary winding creates a line-sensing current (IVSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (RVS1). Minimum tZ (tZ(MIN)) is set at VBULK(MAX) through the RTZ pin. When IVSL is lower than 666 μA, tZ linearly increases and the maximum tZ extension is 140% of tZ(MIN).

UCC28780 TZ-Control.gifFigure 21. tZ Control Optimized for Wide Input Voltage Range

The control law for tD(PWML-H) of UCC28780 is programmable based on the SET pin voltage. When VSET = 0 V, a fixed delay around 40 ns is used to fit a GaN-based ACF with a fast dV/dt on the VSW rising edge. With VSET = 5 V, the dead-time optimization is enabled to intelligently adapt to the effect of nonlinear junction capacitance of Si MOSFETs on the dV/dt of VSW rising edge. The high capacitance region of the COSS curve for the Si QL creates a shallow ramping on VSW after PWML turns off. When COSS of Si QL moves to the low capacitance region with VSW increasing, VSW starts to ramp up very quickly. Since the changing slope varies with different peak magnetizing currents as output load changes, using a fixed dead-time can potentially cause hard-switching on the high-side clamp switch (QH) if the dead-time is not long enough. UCC28780 utilizes the zero crossing detect (ZCD) signal on the auxiliary-winding voltage to identify if VSW overcomes the shallow ramping, and generates a 50-ns delay (tD(VS-PWMH)) before turning on PWMH. This feature allows cycle-by-cycle dead-time adjustment to avoid hard-switching of QH, while providing fast turn-on timing for QH to minimize the body-diode conduction time.

UCC28780 tD(PWML-H).gifFigure 22. tD(PWML-H) Control Optimized for GaN and Si FETs