SLUSD12A October   2017  – February 2018 UCC28780

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. 7.4.10.1 Brown-In and Brown-Out
        2. 7.4.10.2 Output Over-Voltage Protection
        3. 7.4.10.3 Over-Temperature Protection
        4. 7.4.10.4 Programmable Over-Power Protection
        5. 7.4.10.5 Peak Current Limit
        6. 7.4.10.6 Output Short-Circuit Protection
        7. 7.4.10.7 Over-Current Protection
        8. 7.4.10.8 Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. 7.4.11.1 Protections on CS pin Fault
        2. 7.4.11.2 Protections on HVG pin Fault
        3. 7.4.11.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Turns (NP)
          4. 8.2.2.2.4 Secondary Turns (NS)
          5. 8.2.2.2.5 Turns of Auxiliary Winding (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Clamp Capacitor Calculation
        4. 8.2.2.4 Bleed-Resistor Calculation
        5. 8.2.2.5 Output Filter Calculation
        6. 8.2.2.6 Calculation of ZVS Sensing Network
        7. 8.2.2.7 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.5 Output Filter Calculation

The bulk output capacitor of active clamp flyback (ACF) converters, CO1 of the primary-resonance ACF or CO2 of the secondary-resonance ACF, is often determined by the transient-response requirement from no load to full load transition. For a target output voltage undershoot (ΔVO) with the load step-up transient of ΔIO, the minimum bulk output capacitance (CO(MIN)) can be expressed as

Equation 38. UCC28780 Equ-Comin.gif

where tRESP is the time delay from the moment ΔIO is applied to the moment when IFB falls below 1 μA.

The output filter inductor (LO) is an essential component for the secondary-resonance ACF, not only to filter the large switching voltage ripple across CO1 but also to decouple the effect of CO2 on the resonance period. The sum of LO impedance, ESR of CO2 (RCo2), and CO2 impedance at minimum switching frequency (fSW(MIN)) must be much higher than CO1 impedance at the same frequency to force most of switching resonance current to flow through CO1.

Equation 39. UCC28780 Equ-Lo.gif

One benefit of lowering the ESR on CO1 (RCo1) is to help to reduce the switching ripple on the output voltage. Another benefit is reducing the conduction loss of CO1 for the secondary-resonance ACF converter. However, the issue is that the damping between LO and CO1 is weakened. Without proper damping, the magnitude of low-frequency resonance ripple between LO and CO1 enlarges output ripple, affects the loop stability, and affects the operation of synchronous rectifier (QSEC). The secondary-resonance ACF converter is the most vulnerable since CO1 with low capacitance significantly weakens the damping. To resolve this issue, it is found that a serial damping network formed by LDAMP and RDAMP is a very effective way to minimize the impact. However, too strong of a damping design results in noticeable conduction loss increase and full load efficiency drop. Therefore, it is recommended that LDAMP and RDAMP should be higher than the theoretical strong damping value as the following equations suggest. Even though the damping network is an additional component, the physical size or the footprint is much smaller than LO, not only because of the small value but also the wide selection of a small-size chip inductor which winding resistance can be a free RDAMP. For the 45W secondary-resonance ACF design with primary GaN FETs and a polymer-type CO2, when a 0.68-µH chip inductor is in parallel with a 1-µH output filter inductor, there is only 0.15% full-load efficiency drop at 90-V AC input, and there is a negligible efficiency difference at 230-V AC input.

Equation 40. UCC28780 Equ-Ldamp.gif
Equation 41. UCC28780 Equ-Rdamp.gif