7.4.8 Startup Sequence

Figure 29 shows the simplified block diagram related with the VDD startup function of UCC28780, and Figure 30 addresses the startup sequence. The detailed description on the startup waveforms is :

1. Time interval A: The UVLO circuit commands the two internal power-path switches (Q_DDS and Q_DDH) to build connections among SWS, VDD, and HVG pins through two serial current-limiting resistors (R_DDS and R_DDH). The depletion-mode MOSFET (Q_S) starts sourcing charge current (I_SWS) safely from the high-voltage switch-node voltage (V_SW) to the VDD capacitor (C_VDD). Before V_VDD reaches 1 V, I_SWS is limited by the high-resistance R_DDS of 12 kΩ to prevent potential device damage if C_VDD or VDD pin is shorted to ground.
2. Time interval B: After V_VDD rises above 1 V, R_DDS is reduced to a smaller resistance of 1 kΩ. I_SWS is increased to charge C_VDD faster. The maximum charge current during VDD startup can be quantified by Equation 7.
3. Time interval C: As V_VDD reaches V_VDD(ON) of 17.5 V, the ULVO circuit turns-off Q_DDS to disconnect the source pin of Q_S to C_VDD, and turns-off Q_DDH to break the gate-to-source connection of Q_S, so Q_S loses its current-charge capability. V_DD then starts to drop, because the 5-V regulator on REF pin starts to charge up the reference capacitor (C_REF) to 5 V, which maximum charge current (I_SE(REF)) is self-limited at around 14 mA. After V_REF is settled, the UVLO circuit turns-on another power-path switch (Q_11H), so an internal 11-V regulator is connected to the HVG pin. The voltage on the HVG pin capacitor (C_HVG) starts to be discharged by the regulator.
4. Time interval D: During discharging C_HVG of the recommended 2.2 nF, the sink current of the 11-V regulator (I_SE(HVG)) is self-limited at around 90 μA, so it takes longer than 25 μs for settling to 11 V. If V_HVG reaches 11 V in less than 10 to 25 μs, the HVG pin open fault is triggered to protect the device. Once V_HVG is settled to 11 V without the fault event, RUN pin goes high and UCC28780 enters a run state with I_VDD = I_RUN.
5. Time interval E: There is a 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up the gate driver and UCC28780.
6. Time interval F: This is the soft-start region of peak magnetizing current. The first purpose is to limit the supply current if the output is short. The second purpose is to push the switching frequency higher than the audible frequency range during repetitive startup situations. At the beginning of V_O soft-start, the peak current is limited by two V_CST thresholds. The first V_CST startup threshold (V_CST(SM1)) is clamped at 0.28 V and the following second threshold (V_CST(SM2)) is 0.6 V. When V_CST = V_CST(SM1), PWMH is disabled if the VS pin voltage (V_VS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After V_VS exceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from V_CST(SM1) to V_CST(SM2). In case of the inability to build up V_O with V_CST(SM1) at the beginning of the V_O soft-start due to excessively large output capacitor and/or constant-current output load, there is an internal time-out of 1ms to force V_CST to switch to V_CST(SM2).
7. Time interval G: When V_VS rises above 0.6 V, V_CST is allowed to reach V_CST(MAX) of 0.8 V, so the rising rate of V_O startup becomes faster. When PWML is in a high state, I_VDD can be larger than I_RUN, because the 5-V regulator provides the line-sensing current pulse (I_VSL) on the VS pin to sense V_BULK condition.
8. Time interval H: V_O and V_CST settle, and the auxiliary winding takes over the VDD supply. There is a switching ripple on C_HVG during PWML switching, due to the dV/dt coupling of V_SW through the junction capacitance of Q_S. UCC28780 provides an over-voltage protection on HVG pin to avoid the risk of high overshoot under high dV/dt conditions. The over-voltage threshold of HVG pin (V_HVG(OV)) is 13.8V.

Figure 29. Functional Startup Block Diagram

Figure 30. Startup Timing Waveforms