SLUSEP2 December   2021 UCC28781

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Overvoltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 VDD Pin (Device Bias Supply)

The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal references, and the undervoltage lock-out (UVLO) circuit. As shown in Figure 7-5, the UVLO circuit connected to the VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an external depletion-mode MOSFET (QS) to be able to perform both VVDD startup and switch-node voltage (VSW) sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing QS to charge the VDD capacitor (CVDD) from the VSW.

After the VDD startup completes, the ZVS discriminator block and switching logic are enabled. Then, the transformer starts delivering energy to the output capacitor (CO) every switching cycle, so both output voltage (VO) and auxiliary winding voltage (VAUX) increase.

As VAUX is high enough, the auxiliary winding takes over to power VVDD. The UVLO circuit provides a turn-on threshold of VVDD(ON) at 17 V and turn-off threshold of VVDD(OFF) at 10.6 V. For fixed output voltage designs, the wide VVDD range can accommodate lower values of VDD capacitor (CVDD) and support shorter power-on delays.

For a fixed output voltage design, the rectified VAUX is directly connected to the VDD pin. As VVDD reaches VVDD(ON), the SWS pin is disconnected from the VDD pin by the internal power path switch, so the CVDD size has to be sufficient to hold VVDD higher than VVDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power delivery during VO soft start. Therefore, the calculation of minimum capacitance (CVDD(MIN)) needs to consider the discharging effect from the sink current of the UCC28781 during switching in its run state (IRUN(SW)), the average operating current of driver (IDR), and the average gate charge current of half-bridge FETs (IQg) throughout the longest duration of VO soft-start (tSS(MAX)) sequence.

Equation 5. CVDDmin=IRUN(SW)+IDR+IQg×tSSmaxVVDDon×VVDDoff

tSS(MAX) estimation should consider the averaged soft-start current (ISEC(SS)) on the secondary side of the converter, load current on the output (IO(SS)) during start-up (if any), maximum output capacitance (CO(MAX)), and a 0.7-ms time-out potentially being triggered in the startup sequence. Include 1 ms in the equation to be the worst-case condition of the 0.7-ms timer.

Equation 6. tSSmax=CO(max)×VOISECSS-IOSS+1 ms

During the VO soft-start sequence, VCST reaches the maximum current threshold on the CS pin (VCST(MAX)) , so ISEC(SS) at the minimum voltage of the input bulk capacitor (VBULK(MIN)) can be approximated as:

Equation 7. ISECSS=NPS×VCSTmax2×RCS×VBULKminVBULKmin+NPS×VO+VF

where

  • RCS is the current sense resistor
  • NPS is primary-to-secondary turns ratio
  • VF is the forward voltage drop of the secondary rectifier