SLUSEP2 December   2021 UCC28781

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Overvoltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.10 Startup Sequence

Figure 7-35 shows the simplified block diagram related with the VDD startup function of UCC28781, and Figure 7-36 addresses the startup sequence. Table 7-2 describes specific startup waveform time periods.

Figure 7-35 Functional Startup Block Diagram
Figure 7-36 Startup Timing Waveforms
Table 7-2 Startup Time Intervals
TIME PERIOD DESCRIPTION
A The UVLO circuit commands the two internal power-path switches (QDDS and QDDP) to close the connections between SWS, VDD, and P13 pins through two serial current-limiting resistors (RDDS and RDDP). The depletion-mode MOSFET (QS) starts sourcing charge current (ISWS) safely from the high-voltage switch-node voltage (VSW) to the VDD capacitor (CVDD). Before VVDD reaches 1.8 V, ISWS is limited by the high-resistance RDDS of 5 kΩ to prevent potential device damage if CVDD or VDD pin is shorted to ground.
B After VVDD rises above 1.8 V, RDDS is reduced to a smaller resistance of 0.5 kΩ. ISWS is increased to charge CVDD faster. The maximum charge current during VDD startup can be quantified by Equation 8.
C As VVDD reaches VVDD(ON) of 17 V, the ULVO circuit turns-off QDDS to disconnect the source pin of QS to CVDD, and turns-off QDDP to break the gate-to-source connection of QS, so QS loses its current-charge capability. VVDD then starts to drop, because the 5-V regulator on REF pin starts to charge up the reference capacitor (CREF) to 5 V, for which the maximum charge current (ISE(REF)) is self-limited at around 17 mA. After VREF is settled, the UVLO circuit turns-on another power-path switch (QP13), so an internal 13-V regulator is connected to the P13 pin. The voltage on the P13 pin capacitor (CP13) starts to be discharged by the regulator.
D While discharging the recommended 1 µF on CP13 , the sink current of the 13-V regulator (IP13(START)) is self-limited at around 2.2 mA, so it takes longer than 10 μs to settle to 13 V. If VP13 reaches 13 V in less than 10 μs, the P13 pin open fault is triggered to protect the device. Once VP13 has settled to 13 V without the fault event, RUN pin goes high and the controller enters a run state with IVDD = IRUN.
E There is a minimum 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up the isolated gate driver and controller. In this interval, the 2.8-Ω power path switch between the P13 pin and the S13 pin is enabled, so the S13-pin decoupling capacitor (CS13) is charged up and the charge current is supplied from CP13 and the P13 regulator. If 2.2-μs delay is timed out before VS13 reaches to the 10-V power good threshold (VS13_OK), the PWML switching instance is further delayed.
F This is the soft-start region of peak magnetizing current. The first purpose is to limit the supply current if the output is short. The second purpose is to push the switching frequency higher than the audible frequency range during repetitive startup situations. At the beginning of VO soft-start, the peak current is limited by two VCST thresholds. The first VCST startup threshold (VCST(SM1)) is clamped at 0.2 V and the following second threshold (VCST(SM2)) is 0.5 V. When VCST = VCST(SM1), PWMH is disabled if the sampled VS pin voltage (VVS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After the sampled VVS exceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from VCST(SM1) to VCST(SM2). In case of the inability to build up VO with VCST(SM1) at the beginning of the VO soft-start due to excessively large output capacitor and/or constant-current output load, there is an internal time-out of 0.7 ms to force VCST to switch to VCST(SM2).
H When VVS rises above 0.5 V, VCST is allowed to reach VCST(MAX) , so the ramp rate of VO startup becomes faster. When PWML is in a high state, IVDD can be larger than IRUN, because the 5-V regulator provides the line-sensing current pulse (IVSL) on the VS pin to sense VBULK condition.
J When VO gets close to the target regulation level, VCST starts to reduce from VCST(MAX).
K VO and VCST settle, and the auxiliary winding takes over the VDD supply.