Table 2. Design Specification

8.2.1.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the UCC28880 device with the WEBENCH® Power Designer.

1. Start by entering your V_IN, V_OUT and I_OUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
4. In most cases, you will also be able to:
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8.2.1.2.2 Input Stage (R_F, D2, D3, C1, C2, L2)

• Resistor R_F is a flame-proof fusible resistor. R_F limits the inrush current, and also provide protection in case any component failure causes a short circuit. Value for its resistance is generally selected between 4.7 Ω to 15 Ω.
• A half-wave rectifier is chosen and implemented by diode D2 (1N4937). It is a general purpose 1-A, 600-V rated diode. It has a fast reverse recovery time (200 ns) for improved differential-mode-conducted EMI noise performance. Diode D3 (1N4007) is a general purpose 1-A, 1-kV rated diode with standard reverse recovery time (>500 ns), and is added for improved common-mode-conducted EMI noise performance. D3 can be removed and replaced by a short if not needed.
• EMI filtering is implemented by using a single differential-stage filter (C1-L2-C2).

Capacitors C1 and C2 in the EMI filter also acts as storage capacitors for the high-voltage input DC voltage (VIN). The required input capacitor size can be calculated according Equation 2.

Equation 2.

where

• C_BULK(min) is minimum value for the total input capacitor value (C1 + C2 in the schematic of Figure 16).
• RCT = 1 in case a half wave rectifier and RCT = 2 in case of full-wave rectifier (for the schematic reported in Figure 22 RCT = 1 because of a half-wave rectifier).
• P_IN is the converter input power.
• V_IN(min) is the minimum RMS value of the AC input voltage.
• V_BULK(min) is the minimum allowed voltage value across bulk capacitor during converter operation.
• f_LINE(min) is the minimum line frequency when the line voltage is V_IN(min).
• The converter maximum output power is: P_OUT = I_OUT x V_OUT = 0.1 A x 12.5 V = 1.25 W
• Assuming the efficiency η = 68.% the input power is P_IN = P_OUT/η = 1.765 W
• V_BULK(min) = 80 V
• V_IN(min) = 85 V_RMS (from design specification table)
• f_LINE(min) = 57 Hz

C_BULK(min) = 6.96 μF. Considering that electrolytic capacitors, generally used as bulk capacitor, have 20% of tolerance in value, the minimum nominal value required for C_BULK is:

Equation 3.

Select C1 and C2 to be 4.7 μF each (C_BULK = 4.7 μF + 4.7 μF = 9.4 μF > C_BULKn(min)).

By using a full-wave rectifier allows a smaller capacitor for C1 and C2, almost 50% smaller.

8.2.1.2.3 Regulator Capacitor (C_VDD)

Capacitor C_VDD acts as the decoupling capacitor and storage capacitor for the internal regulator. A 100-nF, 10-V rated ceramic capacitor is enough for proper operation of the device's internal LDO.

8.2.1.2.4 Freewheeling Diode (D1)

The freewheeling diode has to be rated for high-voltage with as short as possible reverse-recovery time (t_rr).

The maximum reverse voltage that the diode should experience in the application, during normal operation, is given by Equation 4.

Equation 4.

A margin of 20% is generally considered.

The use of a fast recovery diode is required for the buck-freewheeling rectifier. When designed in CCM, the diode reverse recovery time should be less than 35 ns to keep low reverse recovery current and the switching loss. For example, STTH1R06A provides 25-ns reverse recovery time. When designed in DCM, slower diode can be used, but the reverse recovery time should be kept less than 75 ns. MURS160 can fit the requirement.

8.2.1.2.5 Output Capacitor (CL)

The value of the output capacitor impacts the output ripple. Depending on the combination of capacitor value and equivalent series resistor (R_ESR). A larger capacitor value also has an impact on the start-up time. For a typical application, the capacitor value can start from 47 μF, to hundreds of μF. A guide for sizing the capacitor value can be calculated by the following equations:

Equation 5.

Equation 6.

Take into account that both C_L and R_ESR contribute to output voltage ripple. A first pass capacitance value can be selected and the contribution of C_L and R_ESR to the output voltage ripple can be evaluated. If the total ripple is too high the capacitance value has to increase or R_ESR value must be reduced. In the application example C_L was selected (47 µF) and it has an R_ESR of 0.3 Ω. So the R_ESR contributes for 1/3 of the total ripple. The formula that calculates C_L is based on the assumption that the converter operates in burst of four switching cycles. The number of bursts per cycle could be different, the formula for C_L is a first approximation.

8.2.1.2.6 Load Resistor (R_L)

The resistor should be chosen so that the output current in any standby/no-load condition is higher than the leakage current through the integrated power MOSFET. If the standby load current is ensured to always be larger than the specified I_LEAKAGE, the R_L is not needed. If OVP protection is required for safety reasons, then a zener could be placed across the output (not fitted in the application example). In the application example R_L = 402 kΩ. This ensures a minimum load current of at least ~30 µA when V_OUT = 12 V.

8.2.1.2.7 Inductor (L1)

Initial calculations:

Half of the peak-to-peak ripple current at full load:

Equation 7.

When operating in DCM, the peak-to-peak current ripple is the peak current of the device.

Average MOSFET conduction minimum duty cycle at continuous conduction mode is:

Equation 8.

If the converter operates in discontinuous conduction mode:

Equation 9.

Maximum allowed switching frequency at V_IN(max) and full load:

Equation 10.

Switching frequency has a maximum value limit of f_SW(max).

The worst case I_LIMIT = 140 mA, but assuming ΔI_L = 100 mA.

The converter works in continuous conduction mode (ΔI_L < I_LIMIT) so the

Equation 11.

The maximum allowed switching frequency is 61.7 kHz because the calculated value exceeds it.

Equation 12.

The duty cycle does not force the MOSFET on time to go below t_{ON_TO}. If D_MIN/T_{ON_TO} < f_SW(max), the switching frequency is reduced by current runaway protection and the maximum average switching frequency is lower than f_SW(max), the converter can't support full load.

The minimum inductance value satisfies both the following conditions:

Equation 13.

Equation 14.

In the application example, 2.2 mH is selected as the minimum standard value that satisfy Equation 13 and Equation 14. The value of Equation 14 can be found by characterization graph of Figure 10. Pick the value at the desired maximum junction temperature.

8.2.1.2.8 Feedback Path (Q1, R_FB1, R_FB2)

The feedback path of Q1, R_FB1 and R_FB2 implements a level-shifted direct feedback. R_FB2 sets the current through the feedback path, and R_FB1 sets the output voltage. Q1 acts as the level shifter and needs to be rated for high voltage. The output voltage is determined as follows:

Equation 15.

where

• V_OUT is the output voltage.
• V_{FB_TH} is the FB pin voltage threshold = V_{FB_TH}.
• V_BE is the base-emitter saturation voltage of the external PNP transistor.
• R_FB1 is the external resistor setting the output voltage (depending on the current set by R_FB2, and the V_be).
• R_FB2 is the external resistor setting the current through the external feedback path.

For the application example a target of ~20-μA of current is selected through the external feedback path (I_FB).

Equation 16.

Choose a standard resistor size for R_FB2 = 51 kΩ. For the high-voltage PNP transistor choose a 500-V rated transistor with a V_BE ≈ 0.5 V for the feedback current. To achieve the 12-V output voltage R_FB1 needs to be:

Equation 17.

Choose a standard resistor size for R_FB1 = 591 kΩ.

To change the output voltage, change the value for R_FB1. For example, to target a 5-V output voltage, R_FB1 should be changed to a 230-kΩ resistor.

Accuracy of the output-voltage level depends proportionally on the variation of V_{FB_TH}, and on the absolute accuracy of V_BE according to Equation 16 and Equation 17.

The current through the feedback path is connected over the high voltage input (VIN), and this feedback current is always on. Higher current provides less noise-sensitive feedback, the feedback current should be minimized in order to minimize the total power consumption.

Table 3. Converter Efficiency

Table 4. No-Load and Output-Shorted Converter Input Power

Table 5. Design specification

8.2.2.2.1 Introduction

The low-side buck converter and high-side buck converter design procedures are very similar.

8.2.2.2.2 Feedback Path (C_FB, R_FB1 and R_FB2) and Load Resistor (R_L)

In low-side buck converter the output voltage is always sensed by the FB pin and UCC28880 internal controller can turn on the MOSFET on VOUT. In high-side buck converter applications the information on the output voltage value is stored on C_FB capacitor. This information is not updated in real time. The information on C_FB capacitor is updated just after MOSFET turn-off event. When the MOSFET is turned off, the inductor current forces the freewheeling diode (D1 in Figure 19) to turn on and the GND pin of UCC28880 goes negative at -V_d1 (where V_d1 is the forward drop voltage of diode D1) with respect to the negative terminal of bulk capacitor (C1 in Figure 19). When D1 is on, through diode D4, the C_FB capacitor is charged at V_OUT – V_d4 + V_d1. Set the output voltage regulation level using Equation 18.

Equation 18.

where

• V_{FB_TH} is the FB pin reference voltage.
• V_{OUT_T} is the target output voltage.
• R_FB1, R_FB2 is the resistance of the resistor divider connected with FB pin (see Figure 19)
• The capacitor C_FB after D1 is discharged with a time constant that is τfb = C_FB x (R_FB1 + R_FB2 ).
• Select the time constant τ_FB, given in Equation 19

Equation 19.

The time constant selection leads to a slight output-voltage increase in no-load or light-load conditions. In order to reduce the output-voltage increase, increase τ_FB. The drawback of increasing τ_FB is t in high-load conditions V_OUT could drop.

Table 6. Converter Efficiency

Table 7. No-Load and Output Shorted Converter Input Power