10.3.1 Primary-Side Voltage Regulation

Figure 20 illustrates a flyback converter. The voltage regulation blocks of the device are shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary side control.

Figure 20. Voltage Loop Block Diagram

In primary-side control, the output voltage is sensed by the auxiliary winding during the transfer of transformer energy to the secondary. Figure 21 shows the down slope representing a decreasing total rectifier V_F and the secondary winding resistance voltage drop as the secondary current decreases to 0 A. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the Discriminator Block (Figure 20) reliably ignores the leakage inductance reset and ring, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches 0 current. The internal reference on VS is 4.05 V (V_VSR typical); the resistor divider is selected as outlined in the VS pin description.

Figure 21. Auxiliary Winding Voltage

The UCC28910 VS signal Discriminator Block (Figure 20) ensures accurate sampling time for an accurate sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 22 for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset pedestal, t_{LK_RESET}. Since this can mimic the waveform of the secondary current decay, followed by a sharp down-slope, it is important to keep the leakage reset time less than 500 ns for I_DRAIN minimum, and less than 1.5 μs for I_DRAIN maximum. The second detail is the amplitude of ringing on the auxiliary winding waveform (V_AUX) following t_{LK_RESET}. The peak-to-peak voltage at the VS pin should be less than approximately 100 mV_p-p at least 200 ns before the end of the demagnetization time, t_DMAG. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when t_DMAG is at the minimum. The tolerable ripple on VS is scaled up to the auxiliary winding voltage by R_S1 and R_S2, and is equal to 100 (R_S1 + R_S2) / R_S2 mV.

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode. The internal operating frequency limits of the controller are 115 kHz maximum and 420 Hz minimum. The transformer primary inductance and turns ratio sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. There is no external compensation required for the UCC2891x devices.

Figure 22. VS Voltage

10.3.2 Primary-Side Current Regulation

Timing information at the VS pin and the primary current information allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current is at I_{D_PK(max)} = V_CSTE(max) / R_IPK. Referring to Figure 23, the primary-peak current, turns ratio, secondary demagnetization time (t_DMAG), and switching period (t_SW) establish the secondary average output current. When the average output current reaches the regulation reference in the current control block, the controller operates in frequency modulation mode to control the output current at any output voltage at or below the voltage regulation target as long as the aux winding can keep VDD above the VDD UVLO threshold (VDD_OFF).

Figure 23. Output Current Estimation

Figure 24. Target Output V-I Characteristic

K_CC is defined as the maximum value of the secondary-side conduction duty cycle (D_MAGCC in Figure 23). It is set internally by the UCC2891x and occurs during constant current control mode.

Figure 25. Output Current Control Loop Block Diagram

10.3.3 Voltage Feed Forward Compensation

During normal operation the on-time is determined by sensing the power FET current and switching off the power FET as this current reaches a threshold fixed by the feedback loop according to the load condition. The power FET is not immediately turned off and its current, that is also the primary winding current, continues to rise for some time during the propagation delay (t_DELAY in Figure 26). Keeping the reference for the PWM comparator constant, the value of the primary winding peak current depends on the slope of the primary winding current and t_DELAY. The slope of the primary current is proportional to the flyback stage input voltage (V_BULK)

Figure 26. Propagation Delay Effect on the Primary Current Peak

Equation 4.

Equation 5.

The current loop estimates the output current assuming the primary winding peak current is equal to the I_{PK_TARGET} and compares this estimated current with a reference to obtain the current regulation. Considering, I_{D_PEAK} is different from I_{D_PEAK_TARGET} (see Figure 26) we need to compensate the effect of the propagation delay. The UCC28910 and the UCC28911 incorporate fully-integrated propagation-delay compensation that modifies the switching frequency keeping the output current constant during (CC) Constant Current Mode operation. This function is integrated in the controller and requires no external components. This feature keeps the output current constant despite input voltage variations and primary inductance value spread.

10.3.4 Control Law

During voltage regulation, the device operates in switching frequency modulation mode and primary current peak amplitude modulation mode. The internal operating frequency limits of the device are f_SW(max) and f_SW(min). During constant current regulation the device operates only in frequency modulation mode reducing the switching frequency as the output voltage decreases. Figure 27 shows how the primary peak current and the switching frequency change with respect to changes in load. The solid lines are primary-side peak current and the output voltage, the dotted lines are the switching frequency and output current.

Figure 27. Control Law Profile

10.3.5 Valley Switching

The UCC28910 and the UCC28911 utilize valley switching to reduce switching losses in the MOSFET and minimize the current spike at the FET turn on. The UCC28910 operates in valley switching in almost all load conditions until the V_DS ringing is diminished. By switching at the lowest V_DS voltage the MOSFET turn on dV / dt is minimized which is a benefit to reduce EMI.

Referring to Figure 28, devices will operate in a valley switching mode in most load conditions to switch-on at the lowest available V_DS voltage. According to the load it is established a minimum switching period. The MOSFET is switched-on at the first valley that occurs after this minimum period is elapsed. With this control scheme the device can be turned-on at the first valley that occurs after transformer demagnetization or it can skip some valleys before turn-on operating in this case in the so called valley skipping mode. Valley switching is maintained during constant current regulation to provide improved efficiency and EMI benefits in constant current operation. If for some reason no valley is detected at the end of the t_ZTO time the MOSFET turns-on. In order to guarantee discontinuous mode operation at least the first valley needs to be detected or the Mosfet is not turned-on (see Figure 28).

Figure 28. Valley Skipping

In very light-load or no-load condition the V_DS ringing amplitude is very low and not easy to detect, moreover with very low ringing amplitude there would be no benefit in valley switching so in this condition the valley switching is disabled (see Figure 29). The device switch on the MOSFET as soon the time t_ZTO is elapsed. The t_ZTO timer starts as soon as the minimum switching period is elapsed.

Figure 29. Valley Switching Disable at Light Load

10.3.6 Startup Operation

The UCC28910 and UCC28911 are provided with a high-voltage current source, connected between the DRAIN pin and the VDD pin; this current source is activated when a voltage is applied on DRAIN pin. The current source charges the capacitor connected between VDD and GND increasing the VDD voltage. As VDD exceeds VDD_ON the current source is turned off and the controller internal logic is activated and the device starts switching. If the VDD voltage falls below the VDD_OFF threshold, or a fault condition is detected, the controller stops operation and its current consumption is reduced to I_START or I_FAULT. The high-voltage current source is turned on again when VDD voltage goes below VDD_HV(on) (see Figure 30 for reference).

The initial three cycles are limited to I_{D_PEAK(max)} / 3. This allows sensing any input or output faults with minimal power delivery. After the initial three cycles at I_{D_PEAK(max)} / 3, the controller responds to the condition dictated by the control law.

Figure 30. Start Up and Auto Re-Start Operation

The converter remains in DCM during charging of the output capacitor(s), and operates in constant current mode until the output voltage is in regulation.

To avoid high-power dissipation inside the device, such as in the event that VDD is accidentally shorted to GND, the current provided by the high-voltage current source is reduced (I_CH1) when VDD < 1 V (typical).

10.3.7 Fault Protection

There is comprehensive fault protection incorporated into the UCC2891x. Protection functions include:

• Output Over-Voltage Fault
• Input Under-Voltage Fault
• Primary Over-Current Fault
• VDD Clamp Over Current
• Thermal Shut Down

10.3.8 EMI Dithering

Generally, power supply designs need to pass EMI standard such as EN55022. When the device-controlled Flyback design is used as the auxiliary power supply in a larger system, such as motor drive or home appliance, the EMI filter for the entire system should be enough to filter out the EMI noise created by the Flyback converter. However, when the Flyback is a standalone power supply, the EMI noise becomes a concern.

The EMI noise is normally managed by adding necessary EMI filtering or circuit techniques such as the parasitic capacitor control, snubbering, or transformer EMI noise cancelation windings. Besides these, in both the UCC28910 and UCC28911 devices, the MOSFET switching speed is controlled so that the EMI noise can be minimized. Furthermore, EMI dithering technique is also implemented.

The EMI receiver uses a 9-kHz bandwidth detector to measure the noise energy within that bandwidth. If a power supply switching frequency is slightly changed with time, so that the switching frequency energy can be spread outside 9-kHz band, the measured EMI noise can be smaller. This technique makes it easier to pass the EMI standard. This switching frequency change technique is often called EMI dithering or jittering.

The EMI dithering scheme used in these devices effectively change the switching frequency outside of 9-kHz EMI receiver band, while minimize the output voltage ripple caused by the EMI dithering effect. The frequency modulation is based on a 12-cycle repeat rate. In each 12 switching cycles, there are three groups of 4 switching cycle, with three frequency deviations and three peak current settings. Figure 31 illustrates a group of 4 switching cycles, the center frequency and desired peak current. Figure 32 illustrates a group of reduced switching frequency (–7.5 kHz) with increased peak current (+3.5%) and a group of increased switching frequency (+7.5 kHz) with decreased peak current (–3.5%). The 7.5 kHz frequency deviation is selected to spread the switching frequency noise energy outside of 9-kHz EMI detector bandwidth. In turn, this frequency reduces the measured EMI noise.

Figure 31. EMI Dithering During CV Mode Operation

Figure 32. EMI Dithering During CC Mode Operation

The UCC28910 and UCC28911 devices control the Flyback converter during DCM operation only. The frequency change with fixed peak current may result in output voltage ripple because of the fluctuation of the energy delivery. By adjusting the peak current and frequency at the same time allows minimum variation on the energy delivery and reduces the output voltage ripple. During CC mode operation, the switching frequency is controlled to deliver the constant output current. Therefore, only the peak current is modulated to achieve equivalent EMI dithering.

The EMI dithering is disabled in the light load when the device enters a WAIT state.